Address translation prefetching for input/output devices
AssigneeMicrosoft Technology Licensing, LLC
InventorsRamakrishna Huggahalli, Shachar Raindel
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Abstract
In one example of the present technology, an input/output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.
Claims20
An input/output memory management unit (IOMMU) of a computing device configured to:
- receive a prefetch message comprising a virtual address from a central processing unit (CPU) core;
- receive a translation request comprising the virtual address from an input/output device after receiving the prefetch message from the CPU core;
- perform a page walk on the virtual address through a page table to obtain a prefetched translation of the virtual address to a physical address, wherein the IOMMU begins to perform the page walk prior to receiving the translation request from the input/output device;
- and
- respond to the translation request from the input/output device with the prefetched translation of the virtual address to the physical address.
A computing device comprising:
- a central processing unit (CPU) core;
- a system memory management unit (SMMU) comprising a translation lookaside buffer (TLB);
- a main memory storing a page table;
- and
- an input/output (I/O) device connected to the CPU core and the main memory via an interconnect,
- the CPU core being configured to:
- transmit a direct memory access (DMA) stream setup command to the I/O device, the DMA stream setup command comprising a virtual address;
- and
- transmit a prefetch message to the SMMU, the prefetch message comprising the virtual address included in the DMA stream setup command;
- the SMMU being configured to, in response to the prefetch message:
- prefetch a translation of the virtual address into a physical address;
- and
- receive an address translation request from the I/O device after receiving the prefetch message from the CPU, wherein SMMU begins to perform a page walk through the page table to prefetch the translation of the virtual address prior to receiving the address translation request from the I/O device;
- and
- the I/O device being configured to:
- receive the DMA stream setup command;
- receive the prefetched translation of the virtual address from the SMMU in response to the address translation request to the SMMU;
- and
- execute a DMA operation with the main memory based on the prefetched translation of the virtual address.
A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to prime a translation lookaside buffer (TLB) of an input/output memory management unit (IOMMU) by:
- sending, by a CPU core, a DMA stream setup command to an input/output (I/O) device, the DMA stream setup command comprising a virtual address;
- and
- sending, from the CPU core of the processor, a prefetch message comprising the virtual address to the IOMMU to cause the IOMMU to:
- prefetch a translation of the virtual address into a corresponding physical address;
- receive a translation request comprising the virtual address from the input/output device after receiving the prefetch message from the CPU, wherein the IOMMU begins to perform a page walk to prefetch the translation of the virtual address prior to receiving the translation request from the input/output device;
- and
- respond to the translation request from the input/output device with the prefetched translation of the virtual address to the corresponding physical address.
Dependencies are inferred from the claim text.