Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures

A processor which supports first and second architectures with separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising:

• a memory management unit determining and indicating whether each instruction in memory is of said first or second architecture, said memory management unit further performing address translation from virtual to real addresses for said first and second architectures;
• an instruction decoder directly receiving instructions from memory and decoding said received instructions as belonging to the instruction set of said first or said second architecture depending on an architectural context for each said received instruction;
• and
• control means for detecting and indicating said architectural context of a program being read from memory responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state and controlling said instruction decoder and said memory management unit to dynamically switch between address translation for said first or said second architectures and executing one or more decoded instructions according to said architectural context, wherein said control means comprises:
• an architectural context control mechanism for controlling which architectural context the processor operates under, said architectural context control mechanism controlling an architectural translation method to be used by the memory management unit of the processor when translating an effective address to a virtual address, said architectural context control mechanism further controlling instruction fetch and decode logic of the processor, said architectural context control mechanism further controlling an execution context of process and resources, and said architectural context control mechanism further controlling an interrupt and exception mechanism of the processor, and
• a qualifying mode control mechanism for enabling extensions and limitations to the two architectures, said extensions and limitations allowing a single address translation mechanism to map addresses for one architecture onto translation of addresses of another architecture and a unified interrupt and exception mechanism handling asynchronous interrupts and page translation and protection related exceptions regardless of the architectural context in effect when an interrupt or exception occurs.

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising:

• an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture or being in a second instruction set of said second architecture depending on an architectural context for each said received instruction, wherein said instruction decoder comprises:
• first decoding means for decoding instructions for said first instruction set,
• second decoding means for decoding instructions for said second instruction set, and
• selection means for selecting decoded instructions from said first decoding means or decoded instructions from said second decoding means;
• a memory management unit determining and indicating to which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures;
• and
• control means for detecting and indicating said architectural context of a program being read from memory responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state, said control means controlling the selection means of said instruction decoder and controlling said memory management unit to dynamically switch between address translation for the first or second architectures and executing one or more decoded instructions according to said architectural context.

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes, said processor running under a single multitasking operating system and comprising:

• an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture and a second instruction set of said second architecture depending on an architectural context for each said received instruction;
• a memory management unit determining and providing a page bit indicating to which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures;
• and
• control means for detecting and providing an architecture qualifying bit indicating said architectural context of a program being read from memory responsive to a processor state, said control means and controlling said instruction decoder and said memory management unit to dynamically switch between address translation for the first or second architectures and executing one or more decoded instructions according to said architectural context, wherein said control means comprises a mode control unit which controls the processor state depending on a state of a plurality of bits stored in registers within said processor including an initial stage change bit which determines whether address translation for said second architecture is enabled or disabled, said page bit which indicates whether a current page in memory is for said first or second architectures, and said architecture qualifying bit.

A method implemented in a processor for supporting two separate and distinct instruction-set architectures corresponding to two separate and distinct modes of operation, said processor including an instruction fetch and decode mechanism directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of a first architecture or being in a second instruction set of a second architecture depending on an architectural context for each said received instruction, said processor operating under a single multitasking operating system, said method comprising the steps of:

• determining an operating state from an initial state change indicator, a current page indicator and an architecture qualifying indicator;
• controlling which of first or second architectural translation methods is to be used by a memory management unit when translating an effective address to a virtual address in response to said operating state;
• controlling the instruction fetch and decode mechanism so that instructions of the two different architectures are decoded properly in response to said operating state;
• translating addresses of the two different architectures by mapping the translation of one architecture onto that of another architecture;
• and
• switching from application software written for one architecture to application software written for another architecture in a multitasking environment.

A computer system comprising:

• a microprocessor, said microprocessor supporting two separate and distinct modes of operation corresponding to two separate and distinct instruction-set architectures and running under a single multitasking operating system;
• an external memory device, said external memory device storing application software for said two architectures;
• and
• a system bus connecting said microprocessor to said external memory device;
• said microprocessor having an internal bus connected to said system bus, said microprocessor including:
• an instruction decoder directly receiving instructions from memory and decoding said received instructions as being in a first instruction set of said first architecture or being in a second instruction set of said second architecture depending on an architectural context for each said received instruction;
• a memory management unit determining and providing an indication of which of said first and second architectures each of said directly received instructions belongs and said memory management unit performing address translation from virtual to real addresses for said first and second architectures;
• and
• control means for detecting and indicating said architectural context of a program being read from memory as being either code for said first architecture or code for said second architecture responsive to a processor state, an initial state change indication, said memory management unit indication and said control means indication combining to indicate said processor state, said control means and controlling said instruction decoder and said memory management unit to dynamically switch between said mode of operation corresponding to the first or second architecture and executing one or more decoded instructions according to said architectural context.

A processor which supports first and second architectures having separate and distinct instruction sets and memory management schemes corresponding to two separate and distinct modes of operation, said processor comprising:

• a system interface for connecting to an external memory storing application programs written for said first and second architectures;
• a memory management unit connected to said system interface, said memory management unit reading a page mode control bit from a page table entry for said second architecture;
• an instruction unit including a fetch and decode mechanism, said fetch and decode mechanism including first decoding means for decoding instructions for a first instruction set and mapping decoded instructions to one or more decoded instructions for a second instruction set, second decoding means for decoding instructions for a second instruction set, and selection means for selecting decoded instructions decoded by said first or second decoding means;
• an execution unit connected to receive and execute decoded instructions from said instruction unit, said execution unit having a plurality of registers accessible depending on which of said first or second modes of operation are enabled;
• and
• a mode control unit providing an architecture qualifying bit connected to control said instruction unit and said execution unit, said page mode control bit, an initial change bit and said architecture qualifying bit being supplied to said mode control unit and enabling one of said first or second modes of operation to control address translation and controlling said instruction fetch and decode mechanism of the processor so that instructions of said first and second architectures fetched and aligned for proper decoding.