Amd
Sunnyvale, CA, US· latest recorded location
AMD is named on 11 US grants and 4 published applications in this corpus. Its most frequent classification is H10P (Generic processes or apparatus for the manufacture or treatment of devices covered).
- Granted patents
- 11
- Published applications
- 4
- Inventors
- 49
- Granted in 2026 so far
- 0
- Most recent grant
- 8 Mar 2011
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1997 | 1 | 0 |
| 1998 | 0 | 0 |
| 1999 | 1 | 0 |
| 2000 | 2 | 0 |
| 2001 | 2 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 1 | 0 |
| 2005 | 1 | 0 |
| 2006 | 1 | 1 |
| 2007 | 0 | 0 |
| 2008 | 1 | 0 |
| 2009 | 0 | 2 |
| 2010 | 0 | 1 |
| 2011 | 1 | 0 |
By publication year.
Technology areas
Share of 15 documents
- H10PGeneric processes or apparatus for the manufacture or treatment of devices covered6
- H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by4
- H10DInorganic electric semiconductor devices3
- G06FComputing and data processing2
- G06TImage data processing or generation, in general2
- C09GPolishing compositions1
- C25DProcesses for the electrolytic or electrophoretic production of coatings1
- C25FProcesses for the electrolytic removal of materials from objects1
- H04LDigital communication1
- H04MTelephonic communication1
Recent patents
- Methods for allocating information to system resources using improved mapping8 Mar 2011US 7,903,118 B2
- CMP metal polishing slurry and process with reduced solids concentration25 Nov 2008US 7,456,105 B1
- Capping layer for reducing amorphous carbon contamination of photoresist in semiconductor device manufacture; and process for making same19 Sep 2006US 7,109,101 B1
- Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems14 Jun 2005US 6,905,967 B1
- Integrated circuit structure with dielectric islands in metallized regions10 Feb 2004US 6,690,580 B1
- Etching system and method for forming multiple porous semiconductor regions with different optical and structural properties on a single semiconductor wafer29 Jul 2010US 2010/0187126 A1
- Sige channel epitaxial development for high-k pfet manufacturability16 Jul 2009US 2009/0181507 A1
- Gate stack structure with oxygen gettering layer18 Jun 2009US 2009/0152651 A1
- Methods for allocating information to system resources using improved mapping29 Jun 2006US 2006/0139357 A1
Most cited
By later US patents
- Method and apparatus for hierarchical storage of data for efficient archiving and retrieval of data133US 6,266,679 B12001
- Method and apparatus for automated rework within run-to-run control semiconductor manufacturing72US 6,248,602 B12001
- Copper/low dielectric interconnect formation with reduced electromigration35US 6,096,648 A2000
- Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems22US 6,905,967 B12005
- Set-associative cache memory utilizing a single bank of physical memory16US 5,905,997 A1999