Set-associative cache memory utilizing a single bank of physical memory
AssigneeAmd
InventorDavid R. Stiles
Life of this patent
Estimating the term…
Abstract
Multiple banks associated with a multiple set associative cache are stored in a single chip, reducing the number of SRAMs required. Certain status information for the second level (L2) cache is stored with the status information of the first level cache. This enhances the speed of operations by avoiding a status look-up and modification in the L2 cache during a write operation. In addition, the L2 cache tag address and status bits are stored in a portion of one bank of the L2 data RAMs, further reducing the number of SRAMs required. Finally, the present invention also provides local read-write storage for use by the processor by reserving a number of L2 cache lines.
Claims14
An N-way set-associative cache memory system comprising:
- a semiconductor cache memory chip implementing at least a portion of a single physical bank of cache memory, said cache memory chip being partitioned to contain at least a portion of at least 2 logical banks of data or instructions of said cache memory;
- a part of said memory chip portion of one of said logical banks being allotted to tag address memory for storing tag addresses, said tag addresses corresponding to cached instructions or data allotted to said logical banks at other than the tag address memory allotment, such that at least a section of a first logical bank is allotted for cache tags while all of a second logical bank is allotted for cached instructions or data, such that said section is no more than (N-1)-way set-associative;
- and
- cache control circuitry for addressing said cache memory chip in accordance with bank indication bits, said bank indication bits identifying one of said logical banks wherein cached instructions or data associated with a particular location in main memory may be found.
An N-way set-associative cache memory system including a microprocessor, comprising:
- an array of cache memory;
- an array of tag address memory for storing tag addresses;
- and
- cache control circuitry for addressing said cache memory array in accordance with said tag addresses with a portion of said cache memory array being N-way set-associative for a first type of memory storage, and a second portion of said memory array being no more than (N-1)-way set-associative for a second type of memory storage.
An N-way set-associative cache memory system comprising:
- an array of cache memory;
- an array of tag address memory for storing tag addresses;
- and
- cache control circuitry for addressing said cache memory array in accordance with said tag addresses with a first portion of said cache memory array being N-way set-associative for a first range of memory addresses, and a second portion of said cache memory array being no more than (N-1)-way set-associative for a second range of memory addresses.
Dependencies are inferred from the claim text.