Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems

In the fabrication of a semiconductor wafer feature layer at a stage where circuit features capped with nitride are formed and overlaid with oxide, a process for placing dummy tiles outside the areas containing said circuit features to offset undesired effects during CMP of said feature layer, comprising the steps of:

• creating an isolation zone defined by the area interior of a locus of contour points set at a constant distance from nearest ones of said circuit features;
• creating first through nth tiling zones outside of said isolation zone, the exterior boundary of each successive tiling zone comprising a locus of contour points placed a selected constant threshold distance from nearest ones of said circuit features;
• surveying oxide density and nitride density over the wafer layer outside of said isolation zone;
• based on said survey, developing values of the ratios of oxide/nitride density for each of said first through nth tiling zones;
• using rule-based criteria, determining the placement and sizing of a first set of tiles in said first tiling zone;
• and
• using said oxide/nitride ratio values, determining the placement and sizing of further sets of tiles in the second through said nth tiling zones.

In the fabrication of a semiconductor wafer feature layer at a stage where circuit features capped with nitride are formed and overlaid with conformal oxide trench fill material, a process for placing dummy tiles outside the areas containing said circuit features to offset undesired effects during CMP of said feature layer, comprising the steps of

• surveying said conformal oxide trench fill material density and nitride density over the entire top surface of said wafer feature layer;
• developing values of the ratios of conformal oxide trench fill material/nitride density at two or more specific length scales across the entirety of said feature layer;
• using said ratio values;
• inserting a first set of dummy tiles for local placement with respect to said circuit features in the shortest of said specific length scales;
• and thereafter
• inserting a second set of dummy tiles for regional placement with respect to said circuit feature in at least one of the remaining said length scales,
• wherein tiles greater than 3 um are used where highest nitride/oxide density is needed, and substantially smaller tiles are used where lowest nitride/oxide density is needed.

A semiconductor device comprising a feature layer comprising

• first groups of active features locally aggregated in close mutual proximity;
• second groups of active features separated from said first groups by distances substantially greater than the separation between adjacent features of said first group;
• said active features each having had a nitride capping element and a covering oxide deposition;
• first arrays of dummy tiles disposed within said oxide deposition closely adjacent to each other and to said first groups of active features;
• and
• second arrays of dummy tiles disposed in open areas within said oxide deposition, at separations from said first array determined in part by the measures of the ratio of oxide density to nitride density taken along prescribed survey routes in said open area.

A semiconductor device comprising at least one feature layer comprising:

• circuit features;
• a first set of dummy tiles placed at a selected first length scale in said feature layer outside the areas taken up by said circuit features;
• and a second set of dummy tiles placed at a selected second length scale in said feature layer outside the areas taken up by said circuit features and said first set of dummy tiles;
• said first and said second length scales being chosen in part based on the ratios of oxide/nitride density as measured across the entirety of said feature layer at a selected point in the fabrication of said feature layer of said semiconductor device.