Sige channel epitaxial development for high-k pfet manufacturability

A method comprising:

• patterning a mask over a substrate such that said mask protects N-type areas of said substrate where N-type field effect transistors (NFETs) are to be formed and exposes P-type areas of said substrate where P-type field effect transistors (PFETs) are to be formed;
• epitaxially growing a layer on said P-type areas;
• removing said mask;
• patterning shallow trench isolation (STI) trenches in said N-type areas and said P-type areas, wherein said patterning positions said trenches so as to remove edges of said layer;
• filling said trenches with an isolation material;
• and
• forming said NFETs to have first metal gates and said PFETs to have second metal gates different than said first metal gates.

A method comprising:

• patterning a mask over a Silicon Germanium substrate such that said mask protects N-type areas of said Silicon Germanium substrate where N-type field effect transistors (NFETs) are to be formed and exposes P-type areas of said Silicon Germanium substrate where P-type field effect transistors (PFETs) are to be formed;
• epitaxially growing a Silicon Germanium layer on said P-type areas;
• removing said mask;
• patterning shallow trench isolation (STI) trenches in said N-type areas and said P-type areas, wherein said patterning positions said trenches so as to remove edges of said Silicon Germanium layer;
• filling said trenches with an isolation material;
• and
• forming said NFETs to have first metal gates and said PFETs to have second metal gates different than said first metal gates.