H03L 7/235
Nested phase locked loops
Official title: {Nested phase locked loops}
H03L7/235 (Nested phase locked loops) appears on 149 US grants and 119 published applications in this corpus.
Search patents in H03L- Granted patents
- 149
- Published applications
- 119
- Assignees
- 91
- Inventors
- 250
- Latest grant
- 2 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 3 | 0 |
| 1999 | 0 | 0 |
| 2000 | 2 | 0 |
| 2001 | 2 | 0 |
| 2002 | 1 | 3 |
| 2003 | 4 | 3 |
| 2004 | 2 | 7 |
| 2005 | 0 | 5 |
| 2006 | 6 | 3 |
| 2007 | 5 | 2 |
| 2008 | 3 | 3 |
| 2009 | 5 | 5 |
| 2010 | 3 | 0 |
| 2011 | 4 | 6 |
| 2012 | 2 | 4 |
| 2013 | 9 | 8 |
| 2014 | 11 | 11 |
| 2015 | 14 | 5 |
| 2016 | 4 | 9 |
| 2017 | 13 | 8 |
| 2018 | 9 | 7 |
| 2019 | 11 | 9 |
| 2020 | 7 | 7 |
| 2021 | 3 | 2 |
| 2022 | 4 | 5 |
| 2023 | 1 | 3 |
| 2024 | 6 | 2 |
| 2025 | 2 | 2 |
| 2026 | 1 | 0 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Modified control loop in a digital phase-locked loop2 Jun 2026US 12,647,121 B2Skyworks Solutions, Inc.
- Image synchronization without input clock and data transmission clock in a pulsed laser mapping imaging system14 Oct 2025US 12,440,085 B2Cilag GmbH International
- Clock generation apparatus, clock generation method, adjustment apparatus, adjustment method, and non-transitory computer readable medium12 Aug 2025US 12,388,397 B2Asahi Kasei Microdevices Corporation
- Modified control loop in a digital phase-locked loop10 Dec 2024US 12,166,494 B2
- Delta-sigma modulator with modified quantization error shaping19 Nov 2024US 12,149,252 B2Infineon Technologies AG
- Clock generation apparatus, clock generation method, adjustment apparatus, adjustment method, and non-transitory computer readable medium13 Nov 2025US 2025/0350239 A1Asahi Kasei Microdevices Corporation
- Modified control loop in a digital phase-locked loop15 May 2025US 2025/0158624 A1Skyworks Solutions, Inc.
- Delta-sigma modulator with modified quantization error shaping13 Jun 2024US 2024/0195420 A1Infineon Technologies AG
- Clock generation apparatus, clock generation method, adjustment apparatus, adjustment method, and non-transitory computer readable medium2 May 2024US 2024/0146243 A1Asahi Kasei Microdevices Corporation
- Phase noise performance using multiple resonators with varying quality factors and frequencies13 Jul 2023US 2023/0223944 A1Skyworks Solutions, Inc.
Most cited
By later US patents
- Cascaded PLL for reducing low-frequency drift in holdover mode53US 8,791,734 B1Silicon Laboratories Inc. · 2014
- Method and apparatus for a phase-locked loop circuit with holdover mode51US 5,572,167 ALucent Technologies Inc. · 1996
- Robust clock circuit architecture49US 6,674,332 B1Cypress Semiconductor Corporation · 2004
- Digitally controlled phase locked loop system48US 4,802,009 ARCA Licensing Corporation · 1989
- Flexible phase locked loop system42US 6,104,222 ASony Corporation · 2000