Modified control loop in a digital phase-locked loop

A clock integrated circuit comprising:

• a first phase locked loop configured to generate a first output clock signal using a first input clock signal;
• and
• a second phase locked loop including:
• a variable gain digital filter configured to apply a time-varying gain to a digital signal representative of a second input clock signal to generate a gain-adjusted digital signal;
• a variable gain generator configured to update the time-varying gain based on an estimate error associated with the second input clock signal and a measurement error associated with the second input clock signal;
• and a digitally controlled oscillator configured to generate a feedback signal for the first phase locked loop based on the first output clock signal and the gain-adjusted digital signal.

A phase-locked loop comprising:

• a variable gain digital filter configured to apply a time-varying gain to a digital signal representative of an input clock signal to generate a gain-adjusted digital signal;
• a variable gain generator configured to update the time-varying gain based on an estimate error associated with the input clock signal and a measurement error associated with the input clock signal;
• and
• a digitally controlled oscillator configured to generate an output clock based on a reference signal and the gain-adjusted digital signal.