Method and apparatus for a phase-locked loop circuit with holdover mode

A frequency synthesizer circuit for generating a phase-locked local clock signal without interruption based on a reference clock signal that may be interrupted, the circuit comprising:

• a primary phase-locked loop circuit with an input and an output, the local clock signal being generated at the output;
• a secondary phase-locked loop circuit with an input and an output, the input being connected to the output of the primary loop, the secondary phase-locked loop generating a highly stable scaled output signal of substantially minimal frequency variation that is substantially equal in frequency and substantially in phase with the reference clock signal, wherein the secondary phase-locked loop output signal is partly based on frequency samples over a period of time of the secondary loop output signal;
• and
• a switch adaptable for connecting the input of the primary loop to the reference clock signal or to the output of the secondary loop, wherein the switch operates in a first position to provide the input of the primary loop with the reference clock signal when the reference clock signal is present and wherein the switch operates in a second position to connect the primary loop circuit input to the output of the secondary loop when the reference clock signal is interrupted or absent.