Cascaded PLL for reducing low-frequency drift in holdover mode

A method comprising:

• generating a control signal by a first phase-locked loop (PLL) based on a first clock signal and a first divider value;
• generating the first clock signal by adjusting a controllable oscillator of a second PLL based on a phase difference between a low-jitter clock signal and the first clock signal frequency-divided according to a second divider value;
• and
• generating the second divider value based on a phase difference between a second clock signal and the first clock signal frequency-divided according to a third divider value.

An apparatus comprising:

• means for generating a control signal based on a first clock signal in response to a valid input clock signal and for generating the control signal in an absence of the valid input clock signal;
• means for generating the first clock signal based on a phase difference between a low-jitter reference clock signal and the first clock signal frequency-divided according to a first divider value;
• and
• means for generating the first divider value based on a second clock signal and the first clock signal frequency-divided according to a second divider value.