Robust clock circuit architecture
AssigneeCypress Semiconductor Corporation
InventorsJohn J. Wunner, Galen E. Stansell
Life of this patent
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Abstract
In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.
Claims20
An apparatus comprising:
- a first circuit configured to receive an input signal and a feedback signal and present a reference clock signal based on a difference between the input signal and the feedback signal, the first circuit being configured to continuously present the reference clock signal when the input signal is disrupted;
- and
- a first frequency divider configured to present the feedback signal.
An apparatus comprising:
- a first circuit means for receiving an input signal and a feedback signal and for presenting a reference clock signal, the first circuit means maintaining the reference clock signal in the absence of the input signal;
- a second circuit means for receiving the reference clock signal and for presenting an output clock signal;
- and
- a frequency divider means for presenting the feedback signal.
A method of providing a clock signal, the method comprising:
- presenting a reference clock signal based on a difference between an input reference signal and a divided feedback signal;
- and
- continuing to present the reference clock signal when the input reference signal is disrupted.
Dependencies are inferred from the claim text.