Phase noise performance using multiple resonators with varying quality factors and frequencies

A clock circuit comprising:

• first and second phase locked loops nested together, each including a phase frequency detector configured to supply an error signal, a loop filter configured to output a loop filter output signal based on the error signal, and a feedback divider configured to divide a feedback signal;
• an LC oscillator connected to the loop filter output signal of the first phase locked loop to generate the feedback signal;
• an acoustic wave resonator configured to supply a resonator signal to the first phase locked loop;
• a crystal oscillator configured to supply a crystal oscillator signal to the second phase locked loop;
• and
• a divider control circuit of the second phase locked loop to control the feedback divider of the first phase locked loop based on the loop filter output signal of the second phase locked loop and the divided feedback signal of the first phase locked loop.

A method of operating a clock circuit, the method comprising:

• at a phase frequency detector of a first phase locked loop, receiving a first reference clock signal based on a resonator signal output by an acoustic wave resonator;
• generating a feedback signal based on an LC oscillator signal and a first loop filter output signal generated by a loop filter connected to the first phase frequency detector and on;
• at a phase frequency detector of a second phase locked loop nested with the first phase locked loop, receiving a second reference clock signal based on a crystal oscillator signal;
• at a divider control circuit of the second phase locked loop, outputting a control signal to a feedback divider of the first phase locked loop based on a loop filter output signal of the second phase locked loop and a divided feedback signal of the first phase locked loop.

A clock circuit comprising:

• a plurality of nested phase locked loops;
• a bulk acoustic wave or surface acoustic wave resonator coupled to a first phase locked loop of the plurality of nested phase locked loops;
• a crystal oscillator coupled to a second phase locked loop of the plurality of nested phase locked loops;
• a first feedback divider of the first phase locked loop and a second feedback divider of the second phase locked loop coupled to an LC oscillator of the first phase locked loop;
• and
• a first delta sigma modulator coupled to a loop filter of the second phase locked loop to control the first feedback divider, an update rate of the first phase locked loop being at least an order of magnitude greater than a frequency of the crystal oscillator.