H03H 17/0664
Where the output-delivery frequency is lower than the input sampling frequency, i.e.
Official title: {where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation}
H03H17/0664 (Where the output-delivery frequency is lower than the input sampling frequency, i.e.) appears on 274 US grants and 171 published applications in this corpus.
Search patents in H03H- Granted patents
- 274
- Published applications
- 171
- Assignees
- 165
- Inventors
- 442
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 2 | 0 |
| 1987 | 1 | 0 |
| 1988 | 2 | 0 |
| 1989 | 5 | 0 |
| 1990 | 5 | 0 |
| 1991 | 5 | 0 |
| 1992 | 4 | 0 |
| 1993 | 10 | 0 |
| 1994 | 5 | 0 |
| 1995 | 8 | 0 |
| 1996 | 7 | 0 |
| 1997 | 7 | 0 |
| 1998 | 11 | 0 |
| 1999 | 11 | 0 |
| 2000 | 3 | 0 |
| 2001 | 9 | 0 |
| 2002 | 4 | 5 |
| 2003 | 7 | 5 |
| 2004 | 8 | 12 |
| 2005 | 4 | 7 |
| 2006 | 10 | 9 |
| 2007 | 4 | 4 |
| 2008 | 6 | 5 |
| 2009 | 4 | 4 |
| 2010 | 8 | 4 |
| 2011 | 3 | 6 |
| 2012 | 6 | 2 |
| 2013 | 6 | 3 |
| 2014 | 4 | 0 |
| 2015 | 7 | 4 |
| 2016 | 2 | 2 |
| 2017 | 4 | 7 |
| 2018 | 10 | 6 |
| 2019 | 5 | 8 |
| 2020 | 8 | 18 |
| 2021 | 9 | 11 |
| 2022 | 15 | 15 |
| 2023 | 12 | 14 |
| 2024 | 16 | 12 |
| 2025 | 7 | 3 |
| 2026 | 6 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Signal processing apparatus for generating a plurality of output samples using combiner logic based on a hiearchical tree structure29 Sep 2026US 12,750,040 B2Advantest Corporation
- Method and apparatus for permuting streamed data elements8 Sep 2026US 12,730,758 B2Texas Instruments Incorporated
- Data sensing circuit with parallel digital filter processing18 Aug 2026US 12,712,558 B2Sigmasense, LLC.
- Method and apparatus to sort a vector for a bitonic sorting algorithm5 May 2026US 12,619,553 B2Texas Instruments Incorporated
- Method and apparatus for dual issue multiply instructions10 Mar 2026US 12,572,478 B2Texas Instruments Incorporated
- Sorting vector elements using a mapping of elements21 May 2026US 2026/0140887 A1
- Method and apparatus for implied bit handling in floating point multiplication12 Feb 2026US 2026/0044456 A1Texas Instruments Incorporated
- Permutation for Vector Operations29 Jan 2026US 2026/0030173 A1
- Multiple Multiplication Units in a Data Path15 Jan 2026US 2026/0017207 A1
- Method and Apparatus for Vector Sorting using Vector Permutation Logic8 Jan 2026US 2026/0010485 A1Texas Instruments Incorporated
Most cited
By later US patents
- Sampled data subsampling apparatus110US 4,819,252 AThomson Consumer Electronics, Inc. · 1989
- Variable decimation architecture for a delta-sigma analog-to-digital converter104US 5,157,395 ACrystal Semiconductor Corporation · 1992
- Efficient and scalable FIR filter architecture for decimation98US 6,260,053 B1Cirrus Logic, Inc. · 2001
- Highly integrated scalable, flexible DSP megamodule architecture85US 9,606,803 B2Texas Instruments Incorporated · 2017
- Linear phase FIR sinc filter with multiplexing75US 6,321,246 B1Cirrus Logic, Inc. · 2001