Efficient and scalable FIR filter architecture for decimation

A sigma-delta analog-to-digital converter (ADC) comprising:

• a sigma-delta modulator receiving as input an analog signal, the sigma-delta modulator converting the analog signal into a digital signal having a sampling frequency;
• a decimation filter receiving as input the digital signal from the sigma-delta modulator, the decimation filter reducing the sampling frequency in the digital signal, the decimation filter comprising:
• filter comprising at least one decimation-by-2 processing element, the processing element receiving as input samples of an input signal at a predetermined rate, the processing element providing as output samples of an output signal that is half the predetermined rate, the processing element having a first and second sets of predetermined coefficients, the FIR filter is scalable by connecting a plurality of substantially similar decimation-by-2 processing elements to the at least processing element in series wherein the substantially similar processing elements are configurable to operate independently and in parallel, wherein the first processing element in the series computing a first value based on the first set of predetermined coefficients of the first processing element and the samples of the input signal, if the first processing element is connected to a subsequent neighbor processing element, the first processing element providing the first value to the subsequent neighbor processing element and receiving a second value from the subsequent neighbor processing element, wherein the first processing element computing a third value based on the second value, the second set of predetermined coefficients of the first processing element, and the samples of the input signal, if the first processing element is not connected to a subsequent neighbor processing element, the first processing element computing the third value based on the first value, the second set of predetermined coefficients of the first processing element, and the samples of the input signal, the subsequent neighbor processing element computing a fourth value based on the first value received from the first processing element, a first set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal, if the subsequent neighbor processing element is connected to another subsequent neighbor processing element, the subsequent neighbor processing element providing the fourth value to the another subsequent neighbor processing element and receiving a fifth value from the another subsequent neighbor processing element, the subsequent neighbor processing element computing the second value based on the fifth value, a second set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal, if the subsequent neighbor processing element is not connected to the another subsequent neighbor processing element, the subsequent neighbor processing element computing the second value based on the fourth value, a second set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal;
• a timing and control circuit coupled to the decimation filter, the timing and control circuit providing timing for the digital signal;
• and
• a serial interface circuit coupled to the timing and control circuit, the serial interface circuit allowing the digital signal to be serially communicated to an external device.

A method to provide a scalable FIR filter architecture that requires fewer computations, less storage registers, and is capable of parallel processing, comprising:

• connecting substantially similar decimation-by-2 processing elements in series to provide processing scalability;
• and
• configuring the substantially similar processing elements so that the processing elements operating independently and in parallel;
• wherein each processing element receiving as input samples of an input signal at a predetermined rate, each processing element providing as output samples of an output signal that is half the predetermined rate, each processing element having a first and second sets of predetermined coefficients, the FIR filter is scalable by connecting a plurality of substantially similar decimation-by-2 processing elements to the at least processing element in series wherein the substantially similar processing elements are configurable to operate independently and in parallel, wherein the first processing element in the series computing a first value based on the first set of predetermined coefficients of the first processing element and the samples of the input signal, if the first processing element is connected to a subsequent neighbor processing element, the first processing element providing the first value to the subsequent neighbor processing element and receiving a second value from the subsequent neighbor processing element, wherein the first processing element computing a third value based on the second value, the second set of predetermined coefficients of the first processing element, and the samples of the input signal, if the first processing element is not connected to a subsequent neighbor processing element, the first processing element computing the third value based on the first value, the second set of predetermined coefficients of the first processing element, and the samples of the input signal, the subsequent neighbor processing element computing a fourth value based on the first value received from the first processing element, a first set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal, if the subsequent neighbor processing element is connected to another subsequent neighbor processing element, the subsequent neighbor processing element providing the fourth value to the another subsequent neighbor processing element and receiving a fifth value from the another subsequent neighbor processing element, the subsequent neighbor processing element computing the second value based on the fifth value, a second set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal, if the subsequent neighbor processing element is not connected to the another subsequent neighbor processing element, the subsequent neighbor processing element computing the second value based on the fourth value, a second set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal.