Variable decimation architecture for a delta-sigma analog-to-digital converter

A digital filter for receiving an input digital signal and outputting a decimated digital signal, comprising:

• a single fixed decimation filter section having an input and an output and operating at a fixed decimation ratio and operating at a plurality of different sampling rates for receiving input data at one sampling rate and outputting data at a different sampling rate;
• a clock generator for generating said plurality of sampling rates;
• and
• a controller for processing data through said fixed decimation filter section for a plurality of passes, said controller controlling said clock generator to generate a clock frequency associated with the sampling rate of said fixed decimation filter section during each pass, said controller outputting data from a last of said plurality of passes through said fixed decimation filter section as the output decimated digital signal of the digital filter.

An analog-to-digital converter for receiving an input analog signal and converting it to a digital signal, comprising:

• an analog modulator having an output and for converting an analog input signal to an n-bit digital word, where n is an integer;
• a first digital filter section having a fixed decimation ratio and for decimating the output of said analog modulator from a first sampling frequency to a second sampling frequency that is lower than said first sampling frequency;
• and
• a second digital filter section having a variable decimation ratio selected in response to receiving a configuration control signal, said second digital filter section operable to receive the output of said analog modulator at said second sampling frequency from said first digital filter section and to output a digital signal at a third sampling frequency that is lower than said second sampling frequency by a ratio corresponding to said variable decimation ratio.

A method for digitally filtering an input digital signal to output a decimated digital signal, comprising the steps of:

• providing a first digital filter section;
• decimating the input digital signal from a first sampling frequency to a second sampling frequency in the first digital filter section, the second sampling frequency being lower than the first sampling frequency;
• providing a second digital filter section having a variable decimation ratio;
• selecting the variable decimation ratio in response to receiving a configuration control signal;
• and
• receiving the decimated input signal at the second sampling frequency and outputting a digital signal at a third sampling frequency that is lower than the second sampling frequency by a ratio corresponding to the variable decimation ratio of the second digital filter section.

A method for digitally filtering an input digital signal and outputting a decimated digital signal having associated therewith a decimated sampling frequency, comprising the steps of:

• providing a single fixed decimation filter section having an input and an output and operating at a fixed decimation ratio and operating at a plurality of different sampling rates;
• providing a clock generator for generating the plurality of sampling rates;
• processing data through the fixed decimation filter section for a plurality of passes;
• controlling the clock generator to generate a clock frequency associated with the sampling rate of the fixed decimation filter section during each pass;
• and
• outputting data from a last of the passes to the fixed decimation filter section as the output decimated signal at the decimated sampling frequency.