Method and apparatus for implied bit handling in floating point multiplication

A method comprising:

• decoding, by a decoder, a floating point multiply instruction to generate a decoded floating point multiply instruction;
• and in response to the decoded floating point multiply instruction:
• determining, in a first computational path, values of implied bits of mantissas of floating point numbers and generating first partial product terms;
• multiplying, in a second computational path, remainders of the mantissas to generate second partial product terms;
• detecting, in a third computational path coupled to the first and second computational paths, a number of leading zeros in the mantissas and determining a shift amount for each of the mantissas;
• and
• calculating, exponents for a flush-to-zero mode, in a fourth computational path coupled to the first and second computational paths, exponents for a flush-to-zero mode.

A processor comprising:

• a first slice multiply component and a second slice multiply component, wherein each of the first slice multiply component and the second slice multiply component include a plurality of multiply clusters, wherein each of the plurality of multiply clusters includes:
• a first computational path configurable to determine values of implied bits of mantissas of floating point numbers and generate first partial product terms;
• and
• a second computational path coupled in parallel with the first computational path and configurable to multiply remainders of the mantissas to generate second partial product terms.