Signal processing apparatus for generating a plurality of output samples using combiner logic based on a hiearchical tree structure
AssigneeAdvantest Corporation
InventorChristian Volmer
Life of this patent
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AssigneeAdvantest Corporation
InventorChristian Volmer
Estimating the term…
Embodiments of the present invention provide a digital signal processing apparatus including a combiner logic and a plurality of processing cores. Input samples of the digital signal processing apparatus are provided to the plurality of processing cores. Sets of output samples of the processing cores are provided to the combiner logic as input samples, and the sets of samples are provided to the combiner nodes c of the highest hierarchical level (h=0). A digital signal processing apparatus or a parallel decimating digital convolver may be used as a building block of a signal processor application-specific integrated circuit (ASIC) and/or part of other instruments for generating output samples. Furthermore, applications of the digital signal processing apparatus described herein can be addressed on a parallel DSP, in a response time of real-time or near to real-time, for flexible (or almost arbitrary high) sample rates.
A signal processing apparatus for generating a plurality of output samples based on a plurality of input samples, the signal processing apparatus comprising:
A method of providing a plurality of output samples based on a plurality of input samples, the method comprising:
A non-transitory computer-readable storage medium having embedded therein program instructions, which when executed by one or more processors of a device, causes the device to execute a method of generating a plurality of output samples based on a plurality of input samples, the method comprising:
Dependencies are inferred from the claim text.