Method and apparatus for dual issue multiply instructions
AssigneeTexas Instruments Incorporated
InventorsTimothy David Anderson, Mujibur Rahman
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Abstract
Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication units. The first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. The second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.
Claims20
A processor comprising:
- a first multiplication unit including:
- first multiply circuitry including a first set of outputs;
- and
- first multiplexing logic including a first set of inputs respectively coupled to the first set of outputs;
- and
- a second multiplication unit including:
- second multiply circuitry including a second set of outputs;
- and
- second multiplexing logic including a second set of inputs respectively coupled to the second set of outputs, the second multiplexing logic further including a third set of inputs respectively coupled to the first set of outputs.
A processor comprising:
- a first multiplication unit including:
- a first array of multipliers;
- a first set of multiplexers coupled to the first array of multipliers;
- first carry-save adder circuitry coupled to the first set of multiplexers, the first carry-save adder circuitry having outputs;
- and
- first multiplexing logic coupled to the outputs of the first carry-save adder circuitry;
- wherein the first set of multiplexers is configurable to arrange output values of the first array of multipliers for input to the first carry-save adder circuitry;
- and
- a second multiplication unit including:
- a second array of multipliers;
- a second set of multiplexers coupled to the second array of multipliers;
- second carry-save adder circuitry coupled to the second set of multiplexers, the second carry-save adder circuitry having outputs;
- and
- second multiplexing logic coupled to the outputs of the second carry-save adder circuitry;
- wherein the second set of multiplexers is configurable to arrange output values of the second array of multipliers for input to the second carry-save adder circuitry.
A processor comprising:
- a first multiplication unit including:
- first and second masking logic;
- a first array of multipliers coupled to the first masking logic;
- a second array of multipliers coupled to the second masking logic;
- a first set of multiplexers coupled to the first array of multipliers;
- a second set of multiplexers coupled to the second array of multipliers;
- first adder circuitry coupled to the first set of multiplexers;
- second adder circuitry coupled to the second set of multiplexers;
- and
- first multiplexing logic coupled to the first adder circuitry and coupled to the second adder circuitry;
- communication paths;
- and
- a second multiplication unit coupled to the first multiplexing logic by the communication paths.
Dependencies are inferred from the claim text.