Highly integrated scalable, flexible DSP megamodule architecture

A digital signal processor system comprising:

• a first digital signal processor including
• a first data register file including a plurality of data registers designated by register number storing data;
• an first instruction cache temporarily storing instructions each specifying a data processing operation and at least one data operand by register number,
• a first instruction decoder connected to said first instruction cache for sequentially recalling instructions and determining said specified data processing operation and said specified at least one operand, said instructions including a first stream start instruction and a first stream operand instruction,
• a first data cache connected to an external memory temporarily storing in a plurality of cache lines data,
• at least one first operational unit connected to said first data register file and said first instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said first instruction decoder and storing results in an instruction specified data register,
• a first stream engine connected to said first instruction decoder operable in response to a first stream start instruction to recall from an external memory a first stream of an instruction specified plurality of data elements,
• a first stream head register distinct from said plurality of data registers of said first data register file, connected to said first stream engine and readable by said at least one first operational unit as an operand, said first stream head register sequentially storing a next recalled data element of said first stream of the instruction specified plurality of data elements for use as an operand, and
• wherein said at least one first operational unit is responsive to said first stream operand instruction to receive at least one operand from said first stream head register;
• a second digital signal processor including
• a second data register file including a plurality of data registers designated by register number storing data;
• an second instruction cache temporarily storing instructions each specifying a data processing operation and at least one data operand by register number,
• a second instruction decoder connected to said second instruction cache for sequentially recalling instructions and determining said specified data processing operation and said specified at least one operand, said instructions including a second stream start instruction and a second stream operand instruction
• a second data cache connected to the external memory temporarily storing in a plurality of cache lines data,
• at least one second operational unit connected to said second data register file and said second instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said second instruction decoder and storing results in an instruction specified data register,
• a second stream engine connected to said second instruction decoder operable in response to a second stream start instruction to recall from the external memory a second stream of an instruction specified plurality of data elements,
• a second stream head register distinct from said plurality of data registers of said second data register file, connected to said second stream engine and readable by said at least one second operational unit as an operand, said second stream head register sequentially storing a next recalled data element of said second stream of the instruction specified plurality of data elements for use as an operand, and
• wherein said at least one second operational unit is responsive to said second stream operand instruction to receive at least one operand from said second stream head register;
• and
• a second combined cache connected to said first digital signal processor and said second digital signal processor and adapted for connection to the external memory, said second combined cache operable to service cache misses from said first instruction cache, said first data cache, said second instruction cache and said second data cache from the external memory.

A digital signal processor comprising:

• a data register file including a plurality of data registers designed by register number storing data;
• an instruction memory storing instructions each specifying a data processing operation and at least one data operand by register number;
• an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand, said instructions including a first stream start instruction, a second stream start instruction, a first stream operand instruction and a second stream operand instruction;
• at least one operational unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register;
• a first stream engine connected to said instruction decoder operable in response to a first stream start instruction to recall from an external memory a first stream of an instruction specified plurality of data elements;
• a first stream head register distinct from said plurality of data registers of said data register file, connected to said first stream engine and readable by said at least one operational unit as an operand, said first stream head register sequentially storing a next recalled data element of said first stream of the instruction specified plurality of data elements for use as an operand;
• and
• a second stream engine connected to said instruction decoder operable in response to a second stream start instruction to recall from the external memory a second stream of an instruction specified plurality of data elements;
• a second stream head register distinct from said plurality of data registers of said data register file, connected to said second stream engine and readable by said at least one operational unit as an operand, said second stream head register sequentially storing a next recalled data element of said second stream of the instruction specified plurality of data elements for use as an operand;
• wherein said at least one operational unit is responsive to a first stream operand instruction to receive an operand from said first stream head register;
• and
• wherein said at least one operational unit is responsive to a second stream operand instruction to receive an operand from said second stream head register.