G11C 2211/4062
Parity or ecc in refresh operations
Official title: Parity or ECC in refresh operations
G11C2211/4062 (Parity or ecc in refresh operations) appears on 171 US grants and 199 published applications in this corpus.
Search patents in G11C- Granted patents
- 171
- Published applications
- 199
- Assignees
- 51
- Inventors
- 282
- Latest grant
- 12 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 1 | 3 |
| 2003 | 1 | 2 |
| 2004 | 2 | 5 |
| 2005 | 1 | 8 |
| 2006 | 7 | 16 |
| 2007 | 15 | 6 |
| 2008 | 10 | 9 |
| 2009 | 7 | 5 |
| 2010 | 2 | 2 |
| 2011 | 5 | 7 |
| 2012 | 3 | 3 |
| 2013 | 9 | 4 |
| 2014 | 6 | 14 |
| 2015 | 4 | 3 |
| 2016 | 5 | 4 |
| 2017 | 3 | 9 |
| 2018 | 9 | 8 |
| 2019 | 6 | 11 |
| 2020 | 12 | 10 |
| 2021 | 11 | 18 |
| 2022 | 14 | 15 |
| 2023 | 8 | 9 |
| 2024 | 12 | 12 |
| 2025 | 12 | 9 |
| 2026 | 4 | 7 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor memory device-directed error check and scrub12 May 2026US 12,625,766 B2Micron Technology, Inc.
- Control circuit, control method, and semiconductor memory28 Apr 2026US 12,613,773 B2CXMT Corporation
- Memory device having non-uniform refresh31 Mar 2026US 12,592,272 B2Rambus Inc.
- Methods and apparatus for dynamically adjusting performance of partitioned memory24 Feb 2026US 12,562,206 B2Micron Technology, Inc.
- Apparatus with refresh management mechanism11 Nov 2025US 12,469,539 B2
- Semiconductor memory device-directed error check and scrub17 Sep 2026US 2026/0277742 A1Micron Technology, Inc.
- Methods and apparatus for dynamically adjusting performance of partitioned memory2 Jul 2026US 2026/0188375 A1Micron Technology, Inc.
- Memory with row hammer mitigation technique11 Jun 2026US 2026/0162708 A1SK hynix Inc.
- Internal error-checking circuit and memory4 Jun 2026US 2026/0155195 A1CXMT Corporation
- Memory device with data retention characteristics and operating method thereof16 Apr 2026US 2026/0105951 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Digit line comparison circuits429US 8,279,683 B2Micron Technology, Inc. · 2012
- Dynamic memory architecture employing passive expiration of data96US 7,290,203 B2International Business Machines Corporation · 2007
- Dynamic memory architecture employing passive expiration of data96US 8,020,073 B2International Business Machines Corporation · 2011
- Semiconductor memory and method for operating the same93US 7,203,115 B2Fujitsu Limited · 2007
- Data storing method of dynamic RAM and semiconductor memory device84US 6,697,992 B2Hitachi, Ltd. · 2004