Semiconductor memory device-directed error check and scrub
AssigneeMicron Technology, Inc.
InventorSujeet Ayyapureddi
Life of this patent
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Abstract
Methods, systems, and apparatuses for a memory device (e.g., DRAM) including a directed error check and scrub (ECS) procedure are described. The directed ECS procedure may include read-modify-write cycles when errors are detected in code words. In some embodiments, the memory device may perform the directed ECS procedure on a code word in which an error was previously detected (for example, in response to a read command). The directed ECS procedure described herein may facilitate correcting code word errors before too many errors, exceeding the detection and/or correction capabilities of the memory device, accumulate in the code words.
Claims18
A memory device comprising:
- a memory array comprising a plurality of code words;
- an error-correction code (ECC) circuit coupled with the memory array;
- a mode register configured to store a code word address and a valid indicator;
- and
- circuitry coupled with the memory array, the mode register, and the ECC circuit, the circuitry configured to:
- receive, from a host device, an error check and scrub (ECS) command;
- determine, in response to receiving the ECS command and based on the valid indicator of the mode register, that an error was detected in the memory array prior to receiving the ECS command;
- and
- perform, in response to determining that an error was detected in the memory array prior to receiving the ECS command, an ECS procedure on a code word associated with the error using the ECC circuit, wherein the code word on which the ECS procedure is performed corresponds to the code word address stored in the mode register;
- and
- a Data Mask (DM) pin configured to transmit an indication to the host device that the error was detected.
A method comprising:
- receiving, at a memory device, a read command from a host device coupled to the memory device;
- retrieving, in response to the received read command, data from a memory array of the memory device, wherein the data comprises a code word;
- detecting at least one error in the code word of the retrieved data;
- storing, in response to detecting the at least one error in the code word, a memory array address associated with the code word to a mode register;
- sending, in response to detecting the at least one error in the code word, an indication to the host device that an error was detected in response to the read command, wherein the indication is sent using a Data Mask (DM) pin of the memory device;
- and
- performing an internal read-modify-write cycle on the code word associated with the memory array address in the mode register, wherein the internal read-modify-write cycle comprises correcting the at least one error in the code word.
Dependencies are inferred from the claim text.