Semiconductor memory device-directed error check and scrub
AssigneeMicron Technology, Inc.
InventorSujeet Ayyapureddi
Life of this patent
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Abstract
Methods, systems, and apparatuses for a memory device (e.g., DRAM) including a directed error check and scrub (ECS) procedure are described. The directed ECS procedure may include read-modify-write cycles when errors are detected in code words. In some embodiments, the memory device may perform the directed ECS procedure on a code word in which an error was previously detected (for example, in response to a read command). The directed ECS procedure described herein may facilitate correcting code word errors before too many errors, exceeding the detection and/or correction capabilities of the memory device, accumulate in the code words.
Claims20
A memory device, comprising:
- a memory array comprising a plurality of code words;
- an error-correction code (ECC) circuit coupled with the memory array;
- a mode register configured to store a code word address and a valid indicator;
- and
- circuitry coupled with the memory array, the mode register, and the ECC circuit, the circuitry configured to:
- receive, from a host device, an error check and scrub (ECS) command,
- determine, in response to receiving the ECS command and based on the valid indicator of the mode register, that an error was detected in the memory array prior to receiving the ECS command, and
- perform, using the ECC circuit and in response to determining that an error was detected in the memory array prior to receiving the ECS command, an ECS procedure on a code word corresponding to the code word address stored in the mode register.
A method, comprising:
- receiving, at a memory device, an indication to start an error check and scrub (ECS) procedure;
- determining, based on a valid indicator of a mode register of the memory device, that there is a code word for directed ECS;
- and
- performing, in response to determining that there is a code word for directed ECS, the ECS procedure on a code word corresponding to a code word address stored in the mode register.
A memory device, comprising:
- a memory array comprising a plurality of code words;
- and
- an error check and scrub (ECS) circuit coupled with the memory array, the ECS circuit comprising:
- ECS address counters configured to store an address of a code word in the memory array,
- directed ECS mode registers configured to store code word addresses and valid indicators,
- directed ECS control coupled with the directed ECS mode registers, and
- an ECS multiplexor coupled with the ECS address counters and the directed ECS mode registers, the ECS multiplexor configured to select a code word address from one of the ECS address counters or the directed ECS mode registers based on a determination by the directed ECS control.
Dependencies are inferred from the claim text.