G06F 9/3814
Implementation provisions of instruction buffers
Official title: {Implementation provisions of instruction buffers, e.g. prefetch buffer; banks}
G06F9/3814 (Implementation provisions of instruction buffers) appears on 698 US grants and 532 published applications in this corpus.
Search patents in G06F- Granted patents
- 698
- Published applications
- 532
- Assignees
- 230
- Inventors
- 1,396
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 2 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 8 | 0 |
| 1990 | 4 | 0 |
| 1991 | 8 | 0 |
| 1992 | 3 | 0 |
| 1993 | 9 | 0 |
| 1994 | 5 | 0 |
| 1995 | 13 | 0 |
| 1996 | 16 | 0 |
| 1997 | 23 | 0 |
| 1998 | 31 | 0 |
| 1999 | 26 | 0 |
| 2000 | 16 | 0 |
| 2001 | 21 | 14 |
| 2002 | 22 | 28 |
| 2003 | 17 | 16 |
| 2004 | 26 | 28 |
| 2005 | 22 | 11 |
| 2006 | 24 | 28 |
| 2007 | 19 | 17 |
| 2008 | 19 | 32 |
| 2009 | 16 | 22 |
| 2010 | 15 | 13 |
| 2011 | 10 | 9 |
| 2012 | 18 | 18 |
| 2013 | 12 | 19 |
| 2014 | 14 | 22 |
| 2015 | 16 | 13 |
| 2016 | 22 | 29 |
| 2017 | 23 | 24 |
| 2018 | 25 | 19 |
| 2019 | 23 | 19 |
| 2020 | 35 | 31 |
| 2021 | 23 | 18 |
| 2022 | 29 | 31 |
| 2023 | 23 | 8 |
| 2024 | 16 | 18 |
| 2025 | 25 | 18 |
| 2026 | 9 | 27 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Processor embedded streaming buffer29 Sep 2026US 12,748,592 B2Intel Corporation
- Almost-indirect convolution in quantized neural networks28 Jul 2026US 12,694,262 B2Smart Engines Service, LLC
- Instruction conversion device, instruction conversion method, instruction conversion system, and processor for converting extended instructions based on an emulation flag7 Jul 2026US 12,675,292 B2Shanghai Zhaoxin Semiconductor Co., Ltd.
- Apparatus and method for managing resource30 Jun 2026US 12,670,029 B2Toyota Jidosha Kabushiki Kaisha
- Method and system for assigning instructions to decoders in decoder clusters7 Apr 2026US 12,596,551 B2Hygon Information Technology Co., Ltd.
- Instruction conversion method and processor17 Sep 2026US 2026/0277611 A1Shanghai Zhaoxin Semiconductor Co., Ltd.
- Systems and methods for generating aligned data from segmented data channels17 Sep 2026US 2026/0277613 A1Advanced Micro Devices, Inc.
- Shared dispatch buffer across reservation stations3 Sep 2026US 2026/0259736 A1QUALCOMM Incorporated
- Two-level context caching and eviction for scatter-gather dma3 Sep 2026US 2026/0259842 A1Hewlett Packard Enterprise Development LP
- System on chip, instruction system, compilation system, and related product13 Aug 2026US 2026/0236265 A1Shanghai Cambricon Information Technology Co., Ltd.
Most cited
By later US patents
- High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations320US 5,651,125 AAdvanced Micro Devices, Inc. · 1997
- Cluster architecture for a highly parallel scalar/vector multiprocessor system255US 5,197,130 ASupercomputer Systems Limited Partnership · 1993
- High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution164US 5,560,032 ASeiko Epson Corporation · 1996
- Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus117US 5,179,680 ADigital Equipment Corporation · 1993
- Instruction storage method with a compressed format using a mask word109US 5,057,837 ADigital Equipment Corporation · 1991