Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus

A cache miss engine for

• a data processing system having
• an instruction cache, said instruction cache storing, in a distributed fashion, a plurality of instruction fields making up an instruction word,
• an interleaved memory system comprising a plurality of memory controllers, each controller controlling a plurality of memory banks, and said memory system able to output a plurality of data words each machine cycle,
• at least one control processing unit, and
• said instruction words being stored in a variable length compacted format in said memory system and in a fixed length format in the instruction cache, said variable length format including a decoding key and a plurality of fixed length non-zero instruction fields,
• said cache miss engine comprising
• means for reading said decoding key,
• means for reading said instruction fields in a block mode for transmission to said instruction cache,
• means for decoding said decoding key for generating destination tags for each of said read instruction fields, and
• means for associating a said destination tag with each read instruction field for denoting a storage destination of said instruction field in the distributed instruction cache.