Method and system for assigning instructions to decoders in decoder clusters

A processor, comprising:

• at least a first decoder cluster and a second decoder cluster, the second decoder cluster provided with at least one shared decoder shared by the first decoder cluster, the first decoder cluster corresponding to a first instruction queue and the second decoder cluster corresponding to a second instruction queue other than the first instruction queue, and the first decoder cluster corresponding to a first micro-op queue and the second decoder cluster corresponding to a second micro-op queue other than the first micro-op queue;
• wherein:
• the first decoder cluster comprises a first instruction selection circuit and a plurality of decoders;
• the first instruction selection circuit is configured to:
• select a plurality of instructions from a first instruction queue corresponding to the first decoder cluster;
• and
• in response to a quantity of the plurality of instructions being greater than a quantity of decoders of the first decoder cluster, assign, from the plurality of instructions, first instructions with a quantity corresponding to the quantity of decoders of the first decoder cluster to decoders in the first decoder cluster for decoding, and assign, from the plurality of instructions, at least one second instruction other than the first instructions to the at least one shared decoder for decoding;
• and
• the plurality of decoders are configured to decode the first instructions and write micro-ops obtained by decoding the first instructions into a first micro-op queue corresponding to the first decoder cluster,
• wherein the at least one shared decoder is configured to decode the at least one second instruction and write micro-ops obtained by decoding the at least one second instruction into the first micro-op queue,
• wherein the first instruction selection circuit is further configured to determine the at least one shared decoder in the second decoder cluster being idle based on any one selected from a group consisting of:
• no selectable instructions stored in the second instruction queue corresponding to the second decoder cluster;
• the second micro-op queue corresponding to the second decoder cluster is written full of micro-ops;
• and
• a quantity of the selectable instructions stored in the second instruction queue corresponding to the second decoder cluster is less than a quantity of decoders of the second decoder cluster, and the second micro-op queue is not written full of micro-ops.