G06F 9/3557
Using program counter as base address
Official title: {using program counter as base address}
G06F9/3557 (Using program counter as base address) appears on 88 US grants and 82 published applications in this corpus.
Search patents in G06F- Granted patents
- 88
- Published applications
- 82
- Assignees
- 33
- Inventors
- 149
- Latest grant
- 2 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 6 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 2 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 2 | 0 |
| 2000 | 4 | 0 |
| 2001 | 2 | 0 |
| 2002 | 2 | 3 |
| 2003 | 1 | 0 |
| 2004 | 1 | 0 |
| 2005 | 0 | 1 |
| 2006 | 3 | 0 |
| 2007 | 1 | 0 |
| 2008 | 0 | 2 |
| 2009 | 2 | 2 |
| 2010 | 1 | 2 |
| 2011 | 0 | 0 |
| 2012 | 0 | 1 |
| 2013 | 0 | 1 |
| 2014 | 0 | 1 |
| 2015 | 2 | 8 |
| 2016 | 2 | 3 |
| 2017 | 5 | 30 |
| 2018 | 6 | 6 |
| 2019 | 7 | 4 |
| 2020 | 12 | 5 |
| 2021 | 12 | 4 |
| 2022 | 2 | 4 |
| 2023 | 5 | 1 |
| 2024 | 2 | 2 |
| 2025 | 0 | 0 |
| 2026 | 1 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System and method for addressing data in memory2 Jun 2026US 12,645,457 B2Texas Instruments Incorporated
- Capability-generating address calculating instruction10 Sep 2024US 12,086,593 B2Arm Limited
- Implicit program order7 May 2024US 11,977,891 B2Microsoft Technology Licensing, LLC
- System and method for addressing data in memory5 Dec 2023US 11,836,494 B2Texas Instruments Incorporated
- Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices12 Sep 2023US 11,755,327 B2Microsoft Technology Licensing, LLC
- Hardware assisted instruction prefetch for faster processor cluster low power mode (lpm) exit3 Sep 2026US 2026/0259733 A1QUALCOMM Incorporated
- Multi-taken prediction entries for prediction resumption28 May 2026US 2026/0147573 A1Arm Limited
- Technique for constraining access to memory using capabilities13 Jun 2024US 2024/0193101 A1Arm Limited
- System and method for addressing data in memory28 Mar 2024US 2024/0103863 A1Texas Instruments Incorporated
- Capability-generating address calculating instruction16 Mar 2023US 2023/0085143 A1Arm Limited
Most cited
By later US patents
- Methods and apparatus for instruction addressing in indirect VLIW processors64US 6,356,994 B1BOPS, Inc. · 2002
- Microcomputer having 16 bit fixed length instruction format54US 5,682,545 AHitachi, Ltd. · 1997
- Sequencing and fan-out mechanism for causing a set of at least two sequential instructions to be performed in a dataflow processing computer49US 5,226,131 AThe United States of America as represented by the United States Department of Energy · 1993
- Relocation of instructions that use relative addressing41US 9,329,850 B2International Business Machines Corporation · 2016
- Address generating system33US 4,240,139 ATokyo Shibaura Denki Kabushiki Kaisha · 1980