Implicit program order
AssigneeMicrosoft Technology Licensing, LLC
InventorsDouglas C. Burger, Aaron L. Smith
Life of this patent
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AssigneeMicrosoft Technology Licensing, LLC
InventorsDouglas C. Burger, Aaron L. Smith
Estimating the term…
Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions and generating data indicating a relative order for executing the memory access instructions in the instruction block and scheduling operation of a portion of the instruction block based at least in part on the relative order data. In some examples, a store vector data register can store the generated relative ordering data for use in subsequent instances of the instruction block.
An apparatus comprising memory and one or more processor cores coupled thereto, at least one of the one or more processor cores comprising:
A method of operating a processor, the method comprising:
One or more computer-readable storage media storing computer-readable instructions that, when executed by a processor, cause the processor to perform a method, the computer-readable instructions comprising:
Dependencies are inferred from the claim text.