Capability-generating address calculating instruction
AssigneeArm Limited
InventorLee Douglas Smith
Life of this patent
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AssigneeArm Limited
InventorLee Douglas Smith
Estimating the term…
An apparatus has processing circuitry, an instruction decoder, and capability registers, each capability register to store a capability comprising a pointer and constraint metadata for constraining valid use of the pointer/capability. In response to a capability-generating address calculating instruction specifying an offset value, a reference capability register is selected as one of a program counter capability register and a further capability register. A result capability is generated for which the pointer of the result capability indicates a window address identifying a selected window within an address space, the selected window being offset from a reference window by a number of windows determined based on the offset value of the capability-generating address calculating instruction. The reference window comprises the window comprising an address indicated by the pointer of the reference capability register.
An apparatus comprising:
A data processing method for an apparatus comprising processing circuitry hardware and a plurality of capability registers including a result capability register, each capability register to store a capability comprising a pointer and constraint metadata for constraining valid use of the pointer or the capability, the capability registers including a program counter capability register for which the pointer represents a program counter address indicative of a current point of program flow;
A non-transitory computer-readable storage medium comprising a computer program to control a host data processing apparatus to provide an instruction execution environment for execution of target code, the computer program comprising:
Dependencies are inferred from the claim text.