Address generating system

In a data processor having a main memory;

• a memory address register which is connected to said main memory through a memory bus and to a source bus and in which an address to access said main memory is latched;
• a memory data register which is connected through the memory bus to said main memory and to the source bus and in which data read out from said main memory or to be loaded into the same is latched in accordance with the address latched in said memory address register;
• a program status word which is connected to the source bus and a destination bus and in which interrupt levels and condition flags are set;
• wherein the improvement comprises:
• an instruction buffer register which is connected through the memory bus to said main memory and stores an instruction read out from said main memory, said instruction including a plurality of address modification fields and a field for selecting one of these address modification fields;
• an instruction register which is connected through an instruction buffer bus to said instruction buffer register and stores the instruction;
• instruction judging control means which is connected through the instruction buffer bus to said instruction register and judges the instruction stored in said instruction register to produce microinstructions corresponding to the instruction;
• microprogram control unit connected to said instruction judging control means to control the microinstructions outputted from said instruction judging control means;
• a working register connected to the source bus and the destination bus and used as a temporary buffer in execution of the microinstructions;
• and
• address modifying means for performing a desired address modification on the basis of the result of judgment by said instruction judging control means as to the field for selecting either of the address modification fields.