Hardware assisted instruction prefetch for faster processor cluster low power mode (lpm) exit
AssigneeQUALCOMM Incorporated
InventorsSharath Kumar NAGILLA, Maulik SHAH, Dinesh Kumar CHOUDHARY
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Abstract
Aspects of the disclosure are directed to a deterministic processor cluster instruction cache fetch. In accordance with one aspect, the disclosure includes restoring a system state information from a first random access memory (RAM); issuing a program counter (PC) state as a read address (RA) for a processor in a processor cluster system to execute at least one deterministic level two (L2) cache memory miss; retrieving a memory state data including one or more stored instructions from a main memory; and refilling a level two (L2) cache memory with the one or more stored instructions with the processor in a pre-operational state.
Claims20
A method comprising:
- restoring a system state information from a first random access memory (RAM);
- issuing a program counter (PC) state as a read address (RA) for a processor in a processor cluster system to execute at least one deterministic level two (L2) cache memory miss;
- retrieving a memory state data including one or more stored instructions from a main memory;
- and
- refilling a level two (L2) cache memory with the one or more stored instructions with the processor in a pre-operational state.
An apparatus comprising:
- a processor configured to execute at least one deterministic level 2 (L2) cache memory miss;
- and
- a level 2 (L2) cache memory coupled to the processor, the L2 cache memory configured to be refilled with one or more stored instructions with the processor in a pre-operational state.
A non-transitory computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement a deterministic processor cluster instruction cache fetch, the computer executable code comprising:
- instructions for causing a computer to restore a system state information from a first random access memory (RAM);
- instructions for causing the computer to issue a program counter (PC) state as a read address (RA) for a processor in a processor cluster system to execute at least one deterministic level two (L2) cache memory miss;
- instructions for causing the computer to retrieve a memory state data including one or more stored instructions from a main memory;
- and
- instructions for causing the computer to refill a level two (L2) cache memory with the one or more stored instructions with the processor in a pre-operational state.
Dependencies are inferred from the claim text.