G06F 7/5306
With row wise addition of partial products
Official title: {with row wise addition of partial products (G06F7/5324 takes precedence)}
G06F7/5306 (With row wise addition of partial products) appears on 96 US grants and 46 published applications in this corpus.
Search patents in G06F- Granted patents
- 96
- Published applications
- 46
- Assignees
- 64
- Inventors
- 168
- Latest grant
- 3 Jun 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 2 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 3 | 0 |
| 1985 | 2 | 0 |
| 1986 | 3 | 0 |
| 1987 | 2 | 0 |
| 1988 | 5 | 0 |
| 1989 | 3 | 0 |
| 1990 | 3 | 0 |
| 1991 | 7 | 0 |
| 1992 | 2 | 0 |
| 1993 | 3 | 0 |
| 1994 | 1 | 0 |
| 1995 | 6 | 0 |
| 1996 | 0 | 0 |
| 1997 | 2 | 0 |
| 1998 | 4 | 0 |
| 1999 | 6 | 0 |
| 2000 | 2 | 0 |
| 2001 | 2 | 0 |
| 2002 | 0 | 1 |
| 2003 | 1 | 2 |
| 2004 | 0 | 1 |
| 2005 | 1 | 1 |
| 2006 | 1 | 3 |
| 2007 | 1 | 1 |
| 2008 | 0 | 3 |
| 2009 | 1 | 2 |
| 2010 | 1 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 1 | 1 |
| 2014 | 1 | 4 |
| 2015 | 1 | 2 |
| 2016 | 4 | 3 |
| 2017 | 3 | 1 |
| 2018 | 3 | 0 |
| 2019 | 0 | 5 |
| 2020 | 3 | 4 |
| 2021 | 6 | 1 |
| 2022 | 2 | 3 |
| 2023 | 1 | 4 |
| 2024 | 0 | 2 |
| 2025 | 3 | 1 |
| 2026 | 0 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Compressed wallace trees in FMA circuits3 Jun 2025US 12,321,714 B2Intel Corporation
- Semiconductor device, data generation methods used for the same, and method of controlling the same6 May 2025US 12,293,162 B2Renesas Electronics Corporation
- Multiplier and adder in systolic array14 Jan 2025US 12,197,890 B2Google Inc.
- Controlling carry-save adders in multiplication17 Oct 2023US 11,789,701 B2Arm Limited
- Compute-in-memory (CIM) binary multiplier24 May 2022US 11,340,867 B2QUALCOMM Incorporated
- Multiplier circuit2 Jul 2026US 2026/0186743 A1
- Systems and methods for performing double precision high-speed arithmetic operation2 Jan 2025US 2025/0004719 A1Samsung Electronics Co., Ltd.
- Methods and electronic device for high performance modulo multiplication31 Oct 2024US 2024/0361984 A1Samsung Electronics Co., Ltd.
- Multiply-accumulate circuit and method for performing multiply-accumulate operations5 Sep 2024US 2024/0296012 A1
- Digital in-memory computing macro based on approximate arithmetic hardware24 Aug 2023US 2023/0266943 A1The Trustees of Columbia University in the City of New York
Most cited
By later US patents
- Floating point data processor for high speech operation120US 4,075,704 AFloating Point Systems, Inc. · 1978
- Multiplier-accumulator circuit using latched sums and carries69US 4,736,335 AZoran Corporation · 1988
- Accessing arrangement for interleaved modular memories47US 4,189,767 ABell Telephone Laboratories, Incorporated · 1980
- Low power array multiplier42US 7,546,331 B2QUALCOMM Incorporated · 2009
- Multiple processing cell digital data processor39US 4,533,993 ANational Research Development Corporation · 1985