Back to results
US 12,321,714 B2Granted
Compressed wallace trees in FMA circuits
AssigneeIntel Corporation
InventorsAditya Varma, Mahesh Kumashikar, Michael Espig
Life of this patent
Estimating the term…
Abstract
An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.
Claims21
An apparatus, comprising:
- two or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree comprising:
- multiple 3:2 carry-save adder (CSA) circuits comprising a first 3:2 CSA circuit, a second 3:2 CSA circuit, and a third 3:2 CSA circuit;
- a first 4:2 CSA circuit coupled to receive respective signals from the first 3:2 CSA circuit and the second 3:2 CSA circuit;
- a second 4:2 CSA circuit coupled to receive respective signals from the first 4:2 CSA circuit and the third 3:2 CSA circuit;
- and
- a multiplexer circuit coupled to selectively enable or prevent a communication of a carry signal between two of the multiple 3:2 CSA circuits;
- and
- circuitry coupled to the two or more fractional width FMA circuits to provide one or more fractional width FMA operations through the two or more fractional width FMA circuits.
5 more elements
A method, comprising:
- providing two or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree comprising:
- multiple 3:2 carry-save adder (CSA) circuits comprising a first 3:2 CSA circuit, a second 3:2 CSA circuit, and a third 3:2 CSA circuit;
- a first 4:2 CSA circuit coupled to receive respective signals from the first 3:2 CSA circuit and the second 3:2 CSA circuit;
- a second 4:2 CSA circuit coupled to receive respective signals from the first 4:2 CSA circuit and the third 3:2 CSA circuit;
- and
- a multiplexer circuit coupled to selectively enable or prevent a communication of a carry signal between two of the multiple 3:2 CSA circuits;
- and
- providing one or more fractional width FMA operations through the two or more fractional width FMA circuits.
5 more elements
An apparatus, comprising:
- a processor core;
- a memory;
- and
- a fused multiply-accumulate (FMA) unit coupled to the processor core and the memory, wherein the FMA unit comprises two or more fractional width FMA circuits configured as a shared Wallace tree comprising:
- multiple 3:2 carry-save adder (CSA) circuits comprising a first 3:2 CSA circuit, a second 3:2 CSA circuit, and a third 3:2 CSA circuit;
- a first 4:2 CSA circuit coupled to receive respective signals from the first 3:2 CSA circuit and the second 3:2 CSA circuit;
- a second 4:2 CSA circuit coupled to receive respective signals from the first 4:2 CSA circuit and the third 3:2 CSA circuit;
- and
- a multiplexer circuit coupled to selectively enable or prevent a communication of a carry signal between two of the multiple 3:2 CSA circuits;
- wherein the FMA unit is to provide one or more fractional width FMA operations through the two or more fractional width FMA circuits.
7 more elements
Dependencies are inferred from the claim text.