Multiplier and adder in systolic array

A multiply-and-accumulate (MAC) unit, the MAC unit comprising:

• a first flip/flop configured to load a first number and output the first number;
• a second flip/flop configured to load a multiple number and output the multiple number, the multiple number being the first number multiplied by another number;
• a third flip/flop configured to load a second number and output the second number, wherein the first number and the multiple number are loaded at an increased data rate compared to loading the second number;
• a multiplexer in communication with the first, second, and third flip/flops, the multiplexer configured to:
• receive the first number from the first flip/flop, the multiple number from the second flip/flop, and the second number from the third flip/flop,
• produce a partial product based on the first number, the multiple number, and the second number, and
• output the partial product;
• and an adder in communication with the multiplexer, the adder configured to:
• receive the partial product from the multiplexer and a partial sum number derived from an additional MAC unit,
• add the partial product with the partial sum number to produce a result, and
• output the result.

A method of computing a result of at least one multiply and accumulate operation, the method comprising:

• loading a multiple number using a first flip/flop, the multiple number being a first number multiplied by another number;
• loading a second number using a second flip/flop;
• producing a plurality of partial products based on the multiple number and the second number using a multiplexer;
• receiving the plurality of partial products and a partial sum from an additional MAC unit using at least one carry save adder;
• producing at least two partially summed numbers based on the plurality of partial products and the partial sum using the at least one carry save adder;
• receiving the at least two partially summed numbers using a plurality of parallel segmented adders;
• representing the at least two partially summed numbers as at least three segments;
• and
• respectively performing addition operations in parallel on the at least three segments to generate segmented numbers, wherein combining the segmented numbers forms the result.