Multiplier circuit

A circuit configured to perform a multiplication operation between a first value and a second value, the first and second values each comprising respectively up to a number N of chunks of n bits, n being an integer greater than or equal to 2, and the multiplication being realized within a number of clock cycles depending on the sizes of the first and second values, the circuit comprising:

• a number NMUL of multiplier sub-circuits, NMUL being an integer, the multiplier sub-circuits being configured to generate partial products, each partial product corresponding to a multiplication between one chunk among the chunks of the first value and one chunk among the chunks of the second value;
• an adder part configured to generate an intermediate sum and corresponding excess bit values if any, based on the partial products received from the multiplier sub-circuits, each intermediate sum corresponding to the addition of a group of partial products of same significance;
• an input crossbar circuit configured to select during one clock cycle at least one chunk among the chunks of the first value and at least one chunk among the chunks of the second value and to provide them to at least one of the multiplier sub-circuits;
• a control unit configured to indicate, to the input crossbar circuit, which chunks to supply to which of the multiplier sub-circuits and configured to control the use of the multiplier sub-circuits and consequently the adder part by providing to the multiplier sub-circuits, during at least one clock cycle, chunks involved in partial products of different groups of partial products;
• and
• a parallel adder configured to generate a value corresponding to the product between the first and second values by adding the intermediate sums and the excess bit value generated by the adder part.