Multiplier-accumulator circuit using latched sums and carries

A vector scalar multiplier for two vectors (u.sub.(i), v.sub.(i)), each having the same number (L) of components, each of the components of one vector u.sub.(i) having a number of bits (n) and each of the components of the other vector v.sub.(i) having a number of bits (m), said scalar multiplier comprising

• a plurality of multiplier-accumulator rows (m-1) with each multiplier-accumulator row having a plurality of bit multiplying stages (n+1) with each stage including an adder having two inputs and output, a carry-in and a carry-out, said m-1 rows functioning as a dispersed accumulator of sums of partial products,
• latch means interconnecting the carry-out of adders in a row to the carry-in of another adder in the same row whereby each row produces a partial product,
• latch means interconnecting the output of each adder in a row as an input to an adder in another row for producing partial sums of partial products,
• means for sequentially applying multi-bit components u.sub.(i) of one vector as one of the inputs to adders in all rows, one bit of each component going to one stage in all rows,
• means for sequentially applying the bits of each multi-bit component v.sub.(i) of the other vector to adders in each row, one bit of each component going to all stages in one row, and
• accumulator means including a plurality of adders interconnected with adders of the last multiplier-accumulator row for accumulating the final product of said vector scalar multiplication.

A floating point multiplier-accumulator to compute the dot product for two vectors (u.sub.(i), v.sub.(i)), each having the same number (L) of components and each component having a mantissa and an exponent, each of the components of one vector u.sub.(i) having a number of bits (m) and each of the components of the other vector v.sub.(i) having a number of bits (n), said multiplier-accumulator comprising

• a plurality of multiplier rows with each multiplier row having a plurality of bit multiplying stages, each stage including an adding cell having a plurality of sum inputs, a plurality of carry inputs, a plurality of carry outputs and a sum output, said plurality of multiplier rows functioning as a dispersed accumulator of sums of partial products,
• latch means interconnecting the carry-output of adder cells in a row to the carry input of another adder cell in the same row whereby each row produces a partial product,
• latch means interconnecting the sum outputs of adder cells in a row as inputs to adders in another row for producing partial sums of partial products,
• means for sequentially applying components u.sub.(i) of one vector as one of the inputs to adders in all rows, one bit of each component going to one stage in all rows,
• means for sequentially applying the bits of each mantissa component v.sub.(i) of the other vector to adders in each row, one bit of each mantissa component going to all stages in one row,
• product shift means for receiving a product of each multiplication and shifting the binary point thereof in response to shift control means,
• shift control means for comparing an exponent of an accumulated sum of products with combined exponents of a multiplier component and a multiplicand component for a product and controlling said product shift means, and
• accumulator means for receiving and accumulating the product of each multiplication from said product shift means.