Compute-in-memory (CIM) binary multiplier

A method for binary computation, comprising:

• reading a first computation parameter in a memory cell having at least one of a bit-line or a complementary bit-line;
• providing a second computation parameter to a computation input node of a computation circuit;
• computing a logical operation of the first computation parameter and the second computation parameter via the computation circuit coupled to the bit-line or the complementary bit-line, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node;
• enabling the computation circuit via an enable signal provided to an enable node of an enable circuit, wherein the enable circuit comprises a second NMOS transistor coupled between the adder and the drains of the first NMOS transistor and the first PMOS transistor, a gate of the second NMOS transistor being coupled to the enable node;
• and
• performing, via an adder, an add operation based on a signal at drains of the first NMOS transistor and the first PMOS transistor.