Accessing arrangement for interleaved modular memories

In a modular memory system including any arbitrary number M of modules each having the same plurality of individual storage locations, apparatus connected to receive external physical address signals in a successive sequence to provide substantially uniformly distributed access to all of said modules throughout the sequence, said apparatus comprising:

• means for dividing each physical address by the value of M to produce a mixed number;
• adding means, in circuit with said means for dividing, for increasing said mixed number by 2.sup.-(k+1) where k is the ceiling function of the logarithm of M to the base two, said adding means having an output for producing an internal physical address including a whole number portion and a fractional portion;
• busing means, connected to the output of said adding means, for distributing the internal physical address;
• enabling means associated with each of said modules and connected to said busing means, each of said enabling means having two predetermined values distinct to each module, each of said enabling means comparing the fractional portion of the internal physical address to its two predetermined values for producing an enable output when a match between the fractional portion and one of said predetermined values occurs;
• and
• logic means associated with each of said modules connected to said busing means and said enabling means, said logic means providing access to an individual storage location in a module according to the value of the whole number portion of the internal physical address when said enable output occurs.

A modular memory system having a plurality of M modules each including a plurality of addressable storage locations wherein each of the storage locations is capable of being uniquely accessed externally by the occurrence of a distinct physical address, the system comprising:

• means for receiving an input sequence of M successive physical addresses;
• computation means, connected to said means for receiving, for using each physical address and the value of M to produce a quotient output indicative of a mixed number, said computation means producing a sequence of quotient outputs in response to said input sequence of M successive physical addresses;
• adding means, connected to said computation means, for increasing each quotient output by a constant equal to the value of 2.sup.-(k+1), where k is the ceiling function of the logarithm of M to the base two, to produce each internal physical address having a whole number portion and a fractional portion, said adding means producing a sequence of internal physical addresses in response to said input sequence of M successive physical addresses;
• and
• logical means associated with each of said modules and connected to receive each of said internal physical addresses, each of said logical means storing two predetermined constants distinct to each module for comparing the fractional portion of each internal physical address to produce an enable output when a match occurs, said logical means storing the whole number portion of an internal physical address upon the occurrence of the enable output produced in response to the accompanying fractional portion, said logical means then accessing the associated module at an addressable storage location determined by the value of the stored whole number portion, and the plurality of logical means in response to said input sequence of M successive physical addresses each providing access to a corresponding addressable storage location in a different one of each of said modules for each internal physical address so that the memory cycle intervals of the plurality of modules overlap thereby providing a substantially greater data for said modular memory system in response to said input sequence than for that of a separately occurring input physical address to access an individual storage location.