G06F 5/065
Partitioned buffers
Official title: {Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's}
G06F5/065 (Partitioned buffers) appears on 470 US grants and 297 published applications in this corpus.
Search patents in G06F- Granted patents
- 470
- Published applications
- 297
- Assignees
- 212
- Inventors
- 803
- Latest grant
- 21 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 2 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 2 | 0 |
| 1984 | 1 | 0 |
| 1985 | 3 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 3 | 0 |
| 1989 | 9 | 0 |
| 1990 | 6 | 0 |
| 1991 | 4 | 0 |
| 1992 | 9 | 0 |
| 1993 | 3 | 0 |
| 1994 | 8 | 0 |
| 1995 | 10 | 0 |
| 1996 | 10 | 0 |
| 1997 | 7 | 0 |
| 1998 | 7 | 0 |
| 1999 | 10 | 0 |
| 2000 | 15 | 0 |
| 2001 | 16 | 3 |
| 2002 | 10 | 9 |
| 2003 | 17 | 21 |
| 2004 | 19 | 10 |
| 2005 | 14 | 10 |
| 2006 | 8 | 15 |
| 2007 | 10 | 13 |
| 2008 | 10 | 2 |
| 2009 | 10 | 3 |
| 2010 | 6 | 3 |
| 2011 | 10 | 7 |
| 2012 | 11 | 9 |
| 2013 | 8 | 11 |
| 2014 | 16 | 19 |
| 2015 | 22 | 18 |
| 2016 | 29 | 24 |
| 2017 | 25 | 26 |
| 2018 | 28 | 24 |
| 2019 | 23 | 17 |
| 2020 | 18 | 13 |
| 2021 | 14 | 14 |
| 2022 | 10 | 8 |
| 2023 | 10 | 9 |
| 2024 | 10 | 4 |
| 2025 | 3 | 1 |
| 2026 | 1 | 4 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System for memory mapped hardware first in first out21 Jul 2026US 12,688,008 B1SiPanda Inc.
- Communication chip and data processing method12 Aug 2025US 12,386,588 B2Sanechips Technology Co., Ltd.
- Neural processing device and method for synchronization thereof5 Aug 2025US 12,380,325 B2Rebellions Inc.
- Optimizing power in a memory device1 Jul 2025US 12,346,188 B2Rambus Inc.
- Distributed multi-die protocol application interface19 Nov 2024US 12,147,377 B2Altera Corporation
- Crossing frequency and power domains10 Sep 2026US 2026/0267604 A1Google Inc.
- Clock domain crossing queue structure18 Jun 2026US 2026/0169687 A1Shanghai Zhaoxin Semiconductor Co., Ltd.
- Low latency pcie retimer with skew correction28 May 2026US 2026/0147375 A1Kandou Labs, S.A.
- Latency FIFO circuit and operation method thereof having low power dissipation mechanism21 May 2026US 2026/0140696 A1Realtek Semiconductor Corp.
- Neural processing device and method for synchronization thereof23 Oct 2025US 2025/0328755 A1Rebellions Inc.
Most cited
By later US patents
- Method and apparatus for allocation and management of shared memory with data in memory stored as multiple linked lists205US 5,893,162 ATranSwitch Corporation · 1999
- Multi-port communication network device including common buffer memory with threshold control of port packet counters152US 5,987,507 A3Com Technologies · 1999
- Dynamic buffer allocation for a computer system150US 6,243,769 B1Micron Technology, Inc. · 2001
- Arrangement for storing an information signal in a memory and for retrieving the information signal from said memory147US 6,018,612 AU. S. Philips Corporation · 2000
- System for transferring data using value in hardware FIFO'S unused data start pointer to update virtual FIFO'S start address pointer for fast context switching123US 5,649,230 ASeiko Epson Corporation · 1997