Low latency pcie retimer with skew correction
AssigneeKandou Labs, S.A.
InventorsAlexander Koch Koch, Peter Korger Korger
Life of this patent
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Abstract
Methods and systems are described for calculating lane-to-lane skew parameters from detected alignment symbols during a skew measurement mode of operation, detecting a command to switch from skew measurement mode to a transparent mode of operation, wherein each of the plurality of encoded data streams are routed to respective low-latency CDC FIFOs configured to store the encoded data streams using respective write clocks and to output encoded data streams based on corresponding read clocks, each read clock synchronized to a corresponding write clock, and adjusting a timing of a first encoded data stream relative to a second encoded data stream based on the set of lane-to-lane skew parameters generated in the PCS to reduce lane-to-lane skew.
Claims20
A method comprising:
- decoding, during a skew measurement mode, a plurality of encoded data streams associated with respective lanes of a data link and storing each decoded data stream in corresponding PCS first in first out buffers (FIFOs);
- detecting alignment symbols in each of the plurality of decoded data streams, and synchronously setting read pointers of the PCS FIFOs in each lane to positions corresponding to the detected alignment symbols;
- calculating a set of lane-to-lane skew parameters based at least in part on a latency of each PCS FIFO, the latency of each PCS FIFO associated with a read pointer location with respect to a corresponding write pointer;
- detecting a command to switch from the skew measurement retimer mode to a transparent mode of operation, responsively routing each of the plurality of encoded data streams to respective low-latency CDC FIFOs configured to store the encoded data streams using respective write clocks and outputting the encoded data streams based on corresponding read clocks, each read clock synchronized to a corresponding one of the respective write clocks;
- and
- adjusting a timing of a first encoded data stream relative to a second encoded data stream based on the set of lane-to-lane skew parameters generated in the skew measurement mode to reduce lane-to-lane skew.
An apparatus comprising:
- A physical coding sublayer (PCS) configured to decode, during a skew measurement mode, a plurality of encoded data streams associated with respective lanes of a data link;
- a link adjustment circuit configured to perform lane deskew and rate adaptation on the decoded data streams, the link adjustment circuit comprising:
- PCS first in first out buffers (FIFOs) configured to store each decoded data stream;
- symbol detection logic configured to detect alignment symbols in each of the plurality of decoded data streams;
- and
- a link adjustment control circuit configured to synchronously set read pointers of the PCS FIFO for each lane to positions corresponding to the detected alignment symbols and to calculate a set of lane-to-lane skew parameters based at least in part on latency of each PCS FIFO, the latency of each PCS FIFO associated with a read pointer location with respect to a corresponding write pointer;
- a central processing unit (CPU) configured to detect a command to switch from the skew measurement mode to a transparent mode of operation, wherein each of the plurality of encoded data streams are routed to respective low-latency CDC FIFOs configured to store the encoded data streams using respective write clocks and to output encoded data streams based on corresponding read clocks, each read clock synchronized to a corresponding write clock;
- and
- delay buffers connected to outputs of each low-latency CDC FIFOs configured to adjust a timing of a first encoded data stream relative to a second encoded data stream based on the set of lane-to-lane skew parameters generated in the PCS to reduce lane-to-lane skew.
Dependencies are inferred from the claim text.