US 5,649,230 A · System for transferring data using value in hardware FIFO'S unused data start pointer to update virtual FIFO'S start address pointer for fast context switching

Abstract

A system and method for queuing, control and transfer of data between a host processor and a peripheral processor using an architecture and a data flow strategy of one or more virtual FIFO data structures stored in main memory and a hardware FIFO under control of the host and peripheral processors. One virtual FIFO at a time drives the data FIFO with data. In turn, the data FIFO drives a peripheral device with this data. The host software running on the digital processor controls the loading of data for each process (context) into its associated virtual FIFO. The host processor controls the operation of the peripheral processor and the virtual FIFOs. The peripheral processor controls the flow of data from the data FIFO to the peripheral device, and under control of the host software, the flow of data from the driving virtual FIFO to the data FIFO. Start and end address pointers for each virtual FIFO stored in associated memory block indicate the memory location in the virtual FIFO where data is stored. The peripheral processor also keeps a start address pointer of the memory location of the last unused data then read out of the data FIFO to the peripheral device. These address pointers allow the hardware FIFO to be flushed when a context switch occurs, which can take place before all of the data in the driving virtual FIFO is supplied to the data FIFO, and supplied by the data FIFO to the peripheral device.

Claims33

Dependent claims

A virtual FIFO peripheral interface system for use with a host processor and a peripheral processor in connection with queuing control and transfer of data from the host processor to a peripheral, comprising:

(a) at least one virtual FIFO data structure located in a memory for storing data;
(b) a control addresses block associated with said at least one virtual FIFO data structure for indicating the location of data stored within said at least one virtual FIFO data structure;
(c) a hardware FIFO coupled between said at least one virtual FIFO data structure and the peripheral;
and
(d) a direct memory access (DMA) controller, coupled between said at least one virtual FIFO structure and said hardware FIFO, wherein,
said DMA controller transfers data from said at least one virtual FIFO data structure to said hardware FIFO in response to the host processor;
and
the peripheral processor transfers at least a portion of said data from said hardware FIFO for use by the peripheral and tracks the memory location of unused data remaining in said hardware FIFO by keeping an unused data start pointer for determining the memory location of said unused data remaining in said hardware FIFO;
and wherein the peripheral processor manages a start address pointer in said control addresses block by writing a new start address pointer each time a block of data is transferred from a selected virtual FIFO structure to said hardware FIFO and by updating said start address pointer in said control addresses block based on the value of said unused data start pointer at the time of a context switch.

6 more elements

A method for transferring data between a host processor and a peripheral processor using a virtual FIFO peripheral interface, said virtual FIFO peripheral interface including at least one virtual FIFO data structure for storing data and a control addresses block associated with said at least one virtual FIFO data structure, wherein said control addresses block contains start and end address pointers indicating the location of data stored within said at least one virtual FIFO data structure, said method comprising the steps of:

(1) initializing said start and end address pointers;
(2) selecting one of said at least one virtual FIFO data structures;
(3) storing data in said selected virtual FIFO data structure at a beginning indicated by said start address pointer and changing an end address pointer located in said control addresses block associated with said selected virtual FIFO data structure to indicate the end of said data after said storing;
(4) transferring a block of data, beginning at said start address pointer, from said selected virtual FIFO data structure into a hardware FIFO and changing said start address pointer to indicate data after said block of data which has not yet been transferred to said hardware FIFO;
(5) transferring at least a portion of said block of data from said hardware FIFO for use by a peripheral;
(6) tracking the memory location of unused data in said data block remaining in said hardware FIFO which has not been transferred for use by the peripheral in said transferring step (5), including keeping an unused data start pointer for determining the memory location of unused data items remaining in a said hardware FIFO while said portion of said block of data is transferred from said hardware FIFO to the peripheral;
and
(7) updating a start address pointer based on the value of said unused data start pointer at the time of a context switch.

5 more elements

A virtual FIFO peripheral interface system for use with a host processor and a peripheral processor in providing data for operating multiple context processes to a peripheral, comprising:

a plurality of virtual FIFOs located in a memory;
a plurality of control addresses blocks located in said memory, each virtual FIFO being associated with at least one control addresses block, each control addresses block including a start address pointer and an end address pointer for indicating the memory locations in an associated virtual FIFO where data for a context process is stored;
a hardware FIFO coupled between said virtual FIFOs and the peripheral for receiving and storing data from said virtual FIFOs;
and
a DMA controller coupled between said virtual FIFOs and said hardware FIFO;
wherein said DMA controller includes:
means for selecting one of said virtual FIFOs having a block of data consisting of data items for a first context process, and transferring said block of data from said selected virtual FIFO to said hardware FIFO,
means for keeping a fetch pointer pointing to the memory location of a next data item in said selected virtual FIFO to be transferred to said hardware FIFO after said block of data,
means for keeping an unused data start pointer pointing to the memory location of unused data items remaining in said hardware FIFO while data items in at least a portion of said data block are transferred from said hardware FIFO to the peripheral to execute said first context process in the peripheral,
means for managing said start address pointer associated with said selected virtual FIFO by writing a new start address pointer when the block of data is transferred from said selected virtual FIFO to said hardware FIFO,
means for flushing data from said hardware FIFO when a context switch from said first context process to a second context process occurs, and
means for updating said new start address pointer based on the value of said unused data start pointer at the time of said context switch.

9 more elements

Dependencies are inferred from the claim text.

System for transferring data using value in hardware FIFO'S unused data start pointer to update virtual FIFO'S start address pointer for fast context switching

Life of this patent

System for transferring data using value in hardware FIFO'S unused data start pointer to update virtual FIFO'S start address pointer for fast context switching

Life of this patent

Abstract

Claims33