Crossing frequency and power domains

Abstract

An asynchronous FIFO system (300) for transferring data from a sending power domain (302) to a receiving power domain (304) on a chip includes a plurality of storage elements (308) and a plurality of cycling multiplexors (310, 312) in the sending power domain, a data toggling multiplexor (318) and a plurality of pointer generators (314, 316) in the receiving power domain, and a plurality of level shifters (322a-d) arranged between the cycling multiplexors in the sending power domain (302) and other elements in the receiving power domain, wherein each pointer generator is configured to feed a respective pointer value to a respective cycling multiplexor to cause each cycling multiplexor to forward nonconsecutive data (1, 3, 5, 7 or 0, 2, 4, 6) from the plurality of storage elements (308), and wherein the data toggling multiplexor (318) is configured to read from the plurality of cycling multiplexors (310, 312) in a cycle to reconstruct data (0, 1, 2, 3, 4, 5, 6, 7, 8) in the plurality of storage elements in the receiving power domain.

Dependencies are inferred from the claim text.