Latency FIFO circuit and operation method thereof having low power dissipation mechanism
AssigneeRealtek Semiconductor Corp.
InventorsJEONG-FA SHEU, JHENG-YAN LIOU, YUN-SHENG LIN
Life of this patent
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Abstract
A latency first-in-first-out (FIFO) circuit having a low power dissipation mechanism is provided that includes a counting circuit, FIFO buffers, an input circuit and an output circuit. The counting circuit in turn generates a counting value corresponding to one of reference values in a circular manner. Each of the FIFO buffers corresponds to a corresponding one of the reference values and includes stored data. The input circuit receives and writes the input data to one of the FIFO buffers according to the counting value. The output circuit selects the stored data of one of the FIFO buffers according to the counting value to be outputted as delayed data.
Claims18
A latency first-in-first-out (FIFO) circuit having a low power dissipation mechanism comprising:
- a counting circuit to in turn generate a counting value corresponding to one of a plurality of reference values in a circular manner;
- a plurality of FIFO buffers each corresponding to a corresponding one of the plurality of reference values and having stored data;
- an input circuit to receive input data and write the input data to one of the plurality of FIFO buffers according to the counting value;
- and
- an output circuit to select one of the plurality of FIFO buffers to be a selected FIFO buffer according to the counting value and output the stored data in the selected FIFO buffer to be delayed data.
A latency FIFO circuit operation method having a low power dissipation mechanism comprising:
- in turn generating a counting value corresponding to one of a plurality of reference values in a circular manner by a counting circuit;
- configuring each a plurality of FIFO buffers to correspond to a corresponding reference value one of the plurality of reference values and have stored data;
- receiving input data and writing the input data to one of the plurality of FIFO buffers according to the counting value by an input circuit;
- and
- selecting one of the plurality of FIFO buffers to be a selected FIFO buffer according to the counting value and outputting the stored data in the selected FIFO buffer to be delayed data by an output circuit.
Dependencies are inferred from the claim text.