System for memory mapped hardware first in first out

A system of memory-mapped hardware FIFOs and monotonic state variables, the system comprising:

• any number of memory-mapped hardware FIFOs defined as sets of readable and writable memory-mapped hardware registers, wherein different FIFOs in the system are independent, wherein each FIFO has its own maximum number of entries and element size;
• a memory interface to hardware logic that implements a queue with FIFO semantics, wherein a memory store operation on an address of a memory-mapped register performs an enqueue operation, and a memory load operation performs a dequeue operation;
• a memory interface to hardware logic that implements polling of the memory-mapped hardware FIFOs for readability and writability, wherein a memory load operation on a memory address of a memory-mapped register returns an indication of a set of FIFOs that are readable when at least one element is enqueued, and another memory load operation returns an indication of a set of FIFOs that are writable when a FIFO is not full;
• and any number of memory-mapped monotonic state variables defined as sets of readable and writable memory-mapped hardware registers, wherein different monotonic state variables are defined in pairs such that a value of one variable in the pair is bounded by another in the pair, and wherein values of the monotonic state variables are reset to zero without losing their monotonic property.