G06F 2212/682
Multiprocessor tlb consistency
Official title: Multiprocessor TLB consistency
G06F2212/682 (Multiprocessor tlb consistency) appears on 210 US grants and 174 published applications in this corpus.
Search patents in G06F- Granted patents
- 210
- Published applications
- 174
- Assignees
- 54
- Inventors
- 434
- Latest grant
- 23 Dec 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 2 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 2 | 0 |
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 6 | 0 |
| 2000 | 3 | 0 |
| 2001 | 2 | 0 |
| 2002 | 4 | 3 |
| 2003 | 4 | 1 |
| 2004 | 4 | 8 |
| 2005 | 5 | 3 |
| 2006 | 3 | 6 |
| 2007 | 7 | 5 |
| 2008 | 2 | 3 |
| 2009 | 6 | 2 |
| 2010 | 3 | 1 |
| 2011 | 3 | 3 |
| 2012 | 3 | 2 |
| 2013 | 3 | 1 |
| 2014 | 6 | 17 |
| 2015 | 11 | 12 |
| 2016 | 14 | 16 |
| 2017 | 20 | 24 |
| 2018 | 17 | 10 |
| 2019 | 19 | 19 |
| 2020 | 21 | 11 |
| 2021 | 7 | 5 |
| 2022 | 9 | 6 |
| 2023 | 6 | 2 |
| 2024 | 7 | 6 |
| 2025 | 7 | 7 |
| 2026 | 0 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System and method for dynamic cluster-based cache coherency for multi-core processors23 Dec 2025US 12,505,046 B1Next Silicon Ltd
- Remote cache invalidation2 Dec 2025US 12,487,927 B2Apple Inc.
- Pre-fetching address translation for computation offloading8 Jul 2025US 12,353,333 B2Samsung Electronics Co., Ltd.
- Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices1 Jul 2025US 12,346,264 B2Ampere Computing LLC
- Hybrid scheme for performing translation lookaside buffer (TLB) shootdowns18 Mar 2025US 12,253,956 B2VMware, Inc.
- Remote Cache Invalidation26 Feb 2026US 2026/0056885 A1Apple Inc.
- Multi-core processor-based system implementing directed page table entry invalidation18 Sep 2025US 2025/0291735 A1Ampere Computing LLC
- Memory access method and input/output memory management unit19 Jun 2025US 2025/0199963 A1Cloud Intelligence Assets Holding (Singapore) Private Limited
- Processing of Data Synchronization Barrier Instructions8 May 2025US 2025/0147767 A1Apple Inc.
- Performing instruction fetch pipeline synchronization (ifps) in processor-based devices24 Apr 2025US 2025/0130953 A1Ampere Computing LLC
Most cited
By later US patents
- Computing in parallel processing environments463US 8,738,860 B1Tilera Corporation · 2014
- Selective guest system purge control152US 4,779,188 AInternational Business Machines Corporation · 1988
- Efficient performance based scheduling mechanism for handling multiple TLB operations138US 6,728,800 B1Intel Corporation · 2004
- Using writeable page tables for memory address translation in a hypervisor environment113US 7,814,287 B2XenSource, Inc. · 2010
- Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization98US 6,119,204 AInternational Business Machines Corporation · 2000