Efficient performance based scheduling mechanism for handling multiple TLB operations

An integrated circuit device comprising:

• a translation lookaside buffer to receive a first translation lookaside buffer request and a second translation lookaside buffer request for handling, said first request of a first type and said second request of a second type, said first type having a higher priority than said second type;
• wherein each of said first type and said second type is a data translation lookaside buffer hardware purge/insert, a software purge/insert, an instruction translation lookaside buffer purge/insert, or a translation lookaside shootdown purge;
• and
• a hardware page walker coupled to said translation lookaside buffer, said hardware page walker to prioritize said first request and said second requests.

A system comprising:

• a bus;
• a first processor coupled to said bus, said first processor further comprising:
• a first execution unit;
• and
• a first translation lookaside buffer;
• and
• a second processor coupled to said bus, said second processor further comprising:
• a second execution unit;
• a second translation lookaside buffer, and
• a hardware page walker coupled to said second translation lookaside buffer, said hardware page walker to prioritize a first translation lookaside buffer access request and a second translation lookaside buffer access request, wherein each of said translation lookaside buffer access request is a data translation lookaside buffer hardware purge/insert type, a software purge/insert type, an instruction translation lookaside buffer purge/insert type, or a translation lookaside shootdown purge type.