Processing of Data Synchronization Barrier Instructions

A processor, comprising:

• one or more circuits configured to implement an instruction pipeline configured to:
• receive, from another processor, an indication of a data synchronization barrier (DSB) instruction in the other processor that follows a cache invalidate instruction, wherein execution of the cache invalidate instruction invalidates one or more instructions from an instruction cache of the other processor;
• determine, responsive to receiving the indication of the DSB instruction, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address;
• determine, responsive to determining that the other instruction is pending, whether the other instruction retires;
• and
• provide, responsive to determining that the other instruction retires, an acknowledgement to the other processor in response to the indication of the DSB instruction.

A method, comprising:

• receiving, by a processor from another processor, an indication of a data synchronization barrier (DSB) instruction in the other processor that follows a cache invalidate instruction, wherein execution of the cache invalidate instruction invalidates one or more instructions from an instruction cache of the other processor;
• determining, by the processor responsive to receiving the indication of the DSB instruction, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address;
• and
• responsive to determining that the other instruction is pending, determining, by the processor, whether the other instruction retires;
• and
• responsive to determining that the other instruction retires, providing, by the processor, an acknowledgement to the other processor in response to the indication of the DSB instruction.

A device, comprising:

• a first processor;
• a second processor;
• and
• memory storing program instructions;
• wherein the first processor comprises one or more circuits configured to implement an instruction pipeline, the instruction pipeline configured to:
• receive, from the second processor, an indication of a data synchronization barrier (DSB) instruction in the second processor that follows a cache invalidate instruction, wherein execution of the cache invalidate instruction invalidates one or more instructions from an instruction cache of the second processor;
• determine, responsive to receiving the indication of the DSB instruction, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address;
• determine, responsive to determining that the other instruction is pending, whether the other instruction retires;
• and
• provide, responsive to determining that the other instruction retires, an acknowledgement to the second processor in response to the indication of the DSB instruction.