System and method for dynamic cluster-based cache coherency for multi-core processors

A method for managing cache coherency, comprising:

• for each memory area of a plurality of memory areas, cached in a plurality of cache nodes, each of the plurality of cache nodes associated with at least one of a plurality of processing cores connected to the plurality of memory areas:
• clustering the plurality of processing cores into a plurality of clusters according to at least one memory access metric in relation to the memory area;
• and
• for each cluster of the plurality of clusters, associating the memory area with one of a plurality of caching schemes, wherein the plurality of caching schemes comprises:
• a copying scheme, allowing, when the first processing core accesses the memory area, at least one cache line associated with the memory area and cached in the target cache node to be copied to a new target cache node, of the plurality of cache nodes, local to the first processing core;
• and a redirection scheme, wherein an access to the memory area from the first processing core must be redirected to the target cache node without duplication;
• receiving from a first processing core of the plurality of processing cores a memory access command comprising a memory address associated with a memory area of the plurality of memory areas, where the first processing core is a member of a first cluster for the memory area;
• computing a determination of a target cache node of the plurality of cache nodes according to the memory access command, where the target cache node is associated with a second processing core of the plurality of processing cores;
• and
• accessing the memory area according to the caching scheme associated with the memory area for the first cluster.

A software program product for managing cache coherency, comprising:

• a non-transitory computer readable storage medium;
• first program instructions for:
• for each memory area of a plurality of memory areas, cached in a plurality of cache nodes, each of the plurality of cache nodes associated with at least one of a plurality of processing cores connected to the plurality of memory areas:
• clustering the plurality of processing cores into a plurality of clusters according to at least one memory access metric in relation to the memory area;
• and for each cluster of the plurality of clusters, associating the memory area with one of a plurality of caching schemes, wherein the plurality of caching schemes comprises:
• a copying scheme, allowing, when the first processing core accesses the memory area, at least one cache line associated with the memory area and cached in the target cache node to be copied to a new target cache node, of the plurality of cache nodes, local to the first processing core;
• and a redirection scheme, wherein an access to the memory area from the first processing core must be redirected to the target cache node without duplication;
• second program instructions for:
• receiving from a first processing core of the plurality of processing cores a memory access command comprising a memory address associated with a memory area of the plurality of memory areas, where the first processing core is a member of a first cluster for the memory area;
• third program instructions for:
• computing a determination of a target cache node of the plurality of cache nodes according to the memory access command, where the target cache node is associated with a second processing core of the plurality of processing cores;
• and
• fourth program instructions for:
• accessing the memory area according to the caching scheme associated with the memory area for the first cluster;
• wherein the first, second, third and fourth program instructions are executed by at least one computerized processor from the non-transitory computer readable storage medium.