US 6,119,204 A · Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization

Abstract

A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing. In this manner, the second processor is able to continue normal instruction processing during the process of TLB synchronization.

Claims16

Dependent claims

A method for maintaining translation lookaside buffer (TLB) coherency in a data processing system having at least a first processor and a second processor, said method comprising:

in response to detection by said second processor of a TLB entry invalidation request, marking at least one memory referent instruction being processed by said second processor and invalidating a TLB entry in said second processor;
in response to receipt of a synchronization request at said second processor, indicating to said first processor that said second processor has invalidated said TLB entry if said second processor has completed processing said marked instruction;
and
continuing to process instructions in said second processor during an interval between receipt of said synchronization request and indicating to said first processor that said second processor has invalidated said TLB entry, wherein continuing to process instructions includes fetching instructions for processing.

1 more element

A data processing system, comprising:

a system memory;
at least a first processor and a second processor coupled to said system memory, said second processor including:
instruction processing circuitry that fetches and executes instructions;
a translation lookaside buffer (TLB) for translating addresses, said TLB including a plurality of entries;
means, responsive to detection of a TLB entry invalidation request, for marking at least one memory referent instruction being processed by said second processor and for invalidating a TLB entry in said TLB;
and
means, responsive to receipt of a synchronization request, for indicating to said first processor that said second processor has invalidated said TLB entry if said second processor has completed processing said marked instruction, wherein said instruction processing circuitry continues to process instructions during an interval between receipt of said synchronization request and indicating to said first processor that said second processor has invalidated said TLB entry, and wherein continuing to process instructions includes fetching instructions for processing.

4 more elements

Dependencies are inferred from the claim text.

Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization

Life of this patent

Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization

Life of this patent

Abstract

Claims16