Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices

A processor-based device, comprising:

• means for receiving, from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation;
• means for subsequently receiving an instruction fetch pipeline synchronization (IFPS) request from the issuing processor;
• means for determining that any previously received TLBI requests including the TLBI request have completed, responsive to receiving the IFPS request;
• means for determining that all instructions within a fetch pipeline portion of an instruction processing circuit of a remote processor of a plurality of processors of the processor device that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion to an execution pipeline portion of the instruction processing circuit;
• means for performing a data synchronization barrier (DSB) operation, responsive to determining that all instructions within the fetch pipeline portion that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion to the execution pipeline portion;
• and
• means for issuing a synchronization acknowledgement to the issuing processor.

A method for performing instruction fetch pipeline synchronization (IFPS) in processor-based devices, comprising:

• receiving, by a remote processor of a plurality of processors of a processor-based device from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation;
• subsequently receiving, by the remote processor, an instruction fetch pipeline synchronization (IFPS) request from the issuing processor;
• and
• responsive to receiving the IFPS request:
• determining, by the remote processor, that any previously received TLBI requests including the TLBI request have completed;
• determining, by the remote processor, that all instructions within a fetch pipeline portion of an instruction processing circuit of the remote processor that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion to an execution pipeline portion of the instruction processing circuit;
• and
• responsive to determining that all instructions within the fetch pipeline portion that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion to the execution pipeline portion:
• performing, by the remote processor, a data synchronization barrier (DSB) operation;
• and
• issuing, by the remote processor, a synchronization acknowledgement to the issuing processor.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor of a processor-based device to:

• receive, from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation;
• subsequently receive an instruction fetch pipeline synchronization (IFPS) request from the issuing processor;
• and
• responsive to receiving the IFPS request:
• determine that any previously received TLBI requests including the TLBI request have completed;
• determine that all instructions within a fetch pipeline portion of an instruction processing circuit of a remote processor of a plurality of processors of the processor-based device that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion to an execution pipeline portion of the instruction processing circuit;
• and
• responsive to determining that all instructions within the fetch pipeline portion were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion to the execution pipeline portion:
• perform a data synchronization barrier (DSB) operation;
• and
• issue a synchronization acknowledgement to the issuing processor.