G06F 2207/3864
Clockless, i.e. asynchronous operation used as a design principle
Official title: Clockless, i.e. asynchronous operation used as a design principle (G06F2207/3888 takes precedence)
G06F2207/3864 (Clockless, i.e. asynchronous operation used as a design principle) appears on 16 US grants and 13 published applications in this corpus.
Search patents in G06F- Granted patents
- 16
- Published applications
- 13
- Assignees
- 15
- Inventors
- 37
- Latest grant
- 27 Jun 2023
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 2 |
| 2003 | 1 | 0 |
| 2004 | 0 | 2 |
| 2005 | 1 | 2 |
| 2006 | 1 | 1 |
| 2007 | 0 | 1 |
| 2008 | 1 | 0 |
| 2009 | 0 | 0 |
| 2010 | 2 | 0 |
| 2011 | 0 | 1 |
| 2012 | 0 | 0 |
| 2013 | 1 | 1 |
| 2014 | 3 | 1 |
| 2015 | 0 | 0 |
| 2016 | 1 | 0 |
| 2017 | 1 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 2 |
| 2023 | 2 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Chopper stabilized bias unit element with binary weighted charge transfer capacitors27 Jun 2023US 11,687,738 B2Ceremorphic, Inc.
- Layout structure for shared analog bus in unit element multiplier31 Jan 2023US 11,567,730 B2Ceremorphic, Inc.
- System and method for adaptive power management17 Jan 2017US 9,548,735 B1Maxim Intergrated Products, Inc.
- Operand-optimized asynchronous floating-point units and method of use thereof20 Dec 2016US 9,524,270 B2Cornell University
- Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits28 Oct 2014US 8,872,544 B2The University of North Carolina at Chapel Hill
- Chopper Stabilized Bias Unit Element with Binary Weighted Charge Transfer Capacitors1 Dec 2022US 2022/0383002 A1Redpine Signals, Inc.
- Layout Structure for Shared Analog Bus in Unit Element Multiplier4 Aug 2022US 2022/0244913 A1Redpine Signals, Inc.
- Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits4 Sep 2014US 2014/0247069 A1The University of North Carolina at Chapel Hill
- Operand-optimized asynchronous floating-point units and method of use thereof16 May 2013US 2013/0124592 A1Cornell University
- Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits14 Jul 2011US 2011/0169525 A1The University of North Carolina at Chapel Hill
Most cited
By later US patents
- High-throughput asynchronous dynamic pipelines49US 6,590,424 B2The Trustees of Columbia University in the City of New York · 2003
- Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages16US 6,925,549 B2International Business Machines Corporation · 2005
- Parallel prefix operations in asynchronous processors15US 5,999,961 ACalifornia Institute of Technology · 1999
- Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same12US 8,527,572 B1Xilinx, Inc. · 2013
- Hand-shake type data transfer control circuit10US 4,882,704 AMitsubishi Denki Kabushiki Kaisha · 1989